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C
Cardoso, T., P. Pereira, V. Fernaao Pires, and J. F. Martins, "Android-based m-learning remote system for mobile power quality assessment in large buildings with renewable energies", Power Engineering, Energy and Electrical Drives (POWERENG), 2015 IEEE 5th International Conference on, Riga, Latvia, pp. 431-434, May, 2015. Abstract

Power Quality is a generic term focusing on several issues, going from reliability to the quality of service provided by the energy supplier. It addresses limiting aspects such as harmonic distortion, flicker, sags, swells and transients... It is important for the students to understand the differences between the large amounts of events that fit into poor power quality category. Moreover it is important for them to analyze real time non-laboratory events. To provide this experience to the students this paper presents a remote m-learning experimental system where several types of poor power quality events can be tested. The developed system is based on a power quality analysis distributed network and can be remotely accessed from a remote computer or smart phones.

Cardoso, T., P. Pereira, V. Fernao Pires, and J. F. Martins, "Power quality and long life education", Industrial Electronics (ISIE), 2014 IEEE 23rd International Symposium on, Istanbul - Turkey, pp. 2224 - 2228, 2014/06. Abstract

This paper presents a remote laboratory linked with mobile devices for real data analysis on the field of power quality. A global system was developed from the power quality analyzer into the human machine interface devoted to the m-learning system. This m-learning system is intended to be used in a long life learning perspective. The developed remote laboratory is a good opportunity for people, even without deep knowledge on the field, to learn power quality principles in an applied way. Since the system is based on real data, is a good approach to give trainees practical knowledge on the field.

Coito, F., H. Fino, and P. Pereira, "Variability-Aware Optimization of RF Integrated Inductors in Nanometer-Scale Technologies", Integrated Circuits for Analog Signal Processing, New York, Springer-Verlag, pp. 271-287, 2013. Abstract

Progressive scaling of CMOS technology towards nanoscale regime enables the design of highly integrated systems for the wireless communications market. As technology continues to scale, the variability in process parameters may cause significant deviations in device behaviour. The complexity of designing spiral inductors has lead to the development of multi-objective optimization based design methodologies yielding the generation of Pareto-optimal surfaces. However, the variability of the process parameters is usually ignored, yielding the selection of ideally optimal solutions in detriment of quasi-optimal solutions that may prove to be better, should the robustness against process parameter variation be accounted for. We propose the generation of an extended Pareto front containing both optima and quasi-optima solutions. Finally information on the robustness to process parameter variations, is used for electing the best design solutions.The evaluation of the extended set of sub-optima solutions requires methods capable to find the set of local optima, since solutions that are close to each other in the performance index space may be very distant in the design parameter space.

D
Delgado-Gomes, V., J. A. Oliveira-Lima, J. F. Martins, C. Lima, and P. Pereira, "Towards to a Web Service alert software system for standard electrical protective devices", Intelligent Engineering Systems (INES), 2012 IEEE 16th International Conference on, Lisbon, Portugal, pp. 197 -201, june, 2012. Abstract

Electrical Protective Devices are key elements in the electrical network. Their purpose is to perform fault detection in electric power systems, by analysing power system voltages and currents. In order to achieve a more centralized control, protective devices can be connected using Web Services through a Service-Oriented Architecture (SOA) approach. This work targets planning and specification of a mapping between Abstract Communication Service Interface (ACSI) Reporting and Device Profile for Web Services (DPWS) Eventing to achieve a better protective electrical devices control, obtaining an event based alert software system, replacing conventional polling-based systems.

I
Inacio, D., J. Murta Pina, P. Pereira, A. Pronto, M. Ventim Neves, and A. Alvarez, "Study of an axial flux disc motor with superconductor rotor", Compatibility and Power Electronics (CPE), 2015 9th International Conference on, Costa de Caparica, Portugal , pp. 488-493, June, 2015. Abstract

The integration of high temperature superconductors (HTS) in electrical machines potentially allows reduction in devices dimensions or performance improvement for the same active volume, when compared with their conventional ones. The use of polycrystalline HTS samples allows big bulk samples. An axial disc motor with HTS material or conventional aluminium in the rotor and conventional armature has been designed and developed. This paper describes simulations and laboratory experiments performed at liquid nitrogen temperature (77 K) in order to analyze the motor's behaviour and its electromechanical characteristics and to define an electric equivalent circuit that allows describing its operation. In order to evaluate the superconducting quality of the bulks and flux pinning phenomena, Hall probe mapping system was performed in order to define the field profiles at 77 K for different polar configurations. The analysis of the obtained results allows confirm the flux pinning phenomena, being the entire rotor magnetized and conclude that the motor with the HTS rotor behaves as a conventional hysteresis motor even though with a different nature, while the motor with aluminium rotor behaves as a conventional induction motor. In asynchronous regime, the HTS motor exhibits a constant torque, higher than the conventional aluminium one. For both cases, the developed torque is proportional to the poles pairs.

K
Kchaou, B. O., A. Garbaya, M. Kotti, P. Pereira, M. Fakhfakh, and H. M. Fino, "Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits", Integration, the \{VLSI\} Journal, vol. 55, pp. 220 - 226, 2016. AbstractWebsite

Abstract This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters' variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation \{CMOS\} current conveyor and a \{CMOS\} voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.

Kchaou, O. B., A. Sallem, P. Pereira, M. Fakhfakh, and M. H. Fino, "Multi-objective sensitivity-based optimization of analog circuits exploiting NSGA-II front ranking", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Istanbul, Turkey, pp. 1-4, Sept, 2015. Abstract

This work deals with the multi-objective optimization of analog circuits by generating the Pareto front where elements are low sensitive to parameters' variations. NSGA-II is used for obtaining the non-dominated solutions. Richardson extrapolation technique is used for the in-loop optimization approach for computing partial derivatives and, thus, the solutions' sensitivity. NSGA-II Pareto fronts' intrinsic ranking is exploited for the generation of the new ‘low-sensitive’ Pareto front. The case of the optimal sizing of a CMOS voltage follower is considered to exemplify the proposed approach.

M
Marouani, H., A. Sallem, M. Chaoui, P. Pereira, and N. Masmoudi, "A Robustness Study of Metaheuristics to the Optimal Design of RF Integrated Inductors", 2018 15th International Multi-Conference on Systems, Signals Devices (SSD), pp. 1459-1464, March, 2018. Abstract

In this paper, three metaheuristics are investigated to optimize RF Integrated Inductors; namely Differential Evolution (DE) from the field of evolutionary computation, Gravitational Search Algorithm (GSA) based on the law of gravity and mass interactions and Particle Swarm Optimization (PSO) inspired by swarm behaviors in nature. A particular interest is given to the optimization of RF Integrated Inductors. Performances in terms of optimum quality and computing time of the metaheuristics are checked via three test functions and one application that consist of optimizing performances of characterize integrated inductors based on the double$π$-model.

Martins, J. F., P. Pereira, A. J. Pires, and V. F. Pires, "A new teaching tool to enhance power quality assessment", Industrial Electronics Society, IECON 2015 - 41st Annual Conference of the IEEE, Yokohama, Japan, IEEE-IES, pp. 004158-004162, 9-12 Nov., 2015. Abstract

The study and assessment of Power Quality issues is nowadays a very important subject, particularly regarding Cyber-physical and Industrial Agents based systems, which are extremely sensitive to Power Quality disturbances. Giving students or engineers practical experience in this field requires a large investment from teaching institutions. This paper presents a laboratory device that emulates Power Quality disturbances in order to provide the required experimental expertize in the subject. It addresses limiting aspects such as harmonic distortion, flicker, sags, swells and transients. The developed system presents a good opportunity for technicians, even without deep knowledge on the field of power quality, to learn basic principles and be able to identify Power Quality events. Since the system is based on real data, represents a valuable approach giving trainees practical knowledge on the field.

Murta-Pina, J., P. Pereira, J. M. Ceballos, A. Alvarez, N. Amaro, A. Pronto, J. Silva, and P. Arsenio, "Validation and Application of Sand Pile Modeling of Multiseeded HTS Bulk Superconductors", Applied Superconductivity, IEEE Transactions on, vol. 25, no. 3, pp. 1-5, June, 2015. AbstractWebsite

Sand pile and Bean models have already been applied to describe single grain HTS bulks. An extension to that approach was used to model multiseed bulks, needed for several practical applications as electric motors or flywheels with superconducting bearings. The use of genetic algorithms was then proposed to determine intra- and intergrain current densities, and application to two and three seeds samples using trapped flux experimental measurements was exemplified. However, this model assumed some simplifications, as equal properties in grain boundaries between neighboring grains. In this paper an extension to this methodology is proposed and evaluated by analyzing measurements performed in plans at different distances from surfaces of samples with three seeds. Discussion of its influence on a practical application is also explored.

P
Paiva, L., P. Pereira, B. Almeida, P. Maló, J. Hyvärinen, K. Klobut, V. Dimitriou, and T. Hassan, "Interoperability: A Data Conversion Framework to Support Energy Simulation", Sustainable Places 2017, vol. 1, no. 7, 2017. Abstract

In this paper an interoperability solution is proposed, aiming to go from (building) construction models to energy simulation. Moreover, the energy simulation results will feed the KPI’s analysis of a designed building. The proposed solution will be used to translate different data formats allowing the communication between different systems in an automated environment. The solution presented in this paper exploits the concept of Plug’n’Interoperate (PnI), that is supported by the principle of self-configuration as to automate, as much as possible, the configuration and participation of systems into a shared interoperability environment. In order to validate this approach two different scenarios were taken into account, translating from a CAD (Computer- Aided Design) model data format to an energy simulation data format.

Pereira, P., M. Helena Fino, F. Coito, and M. Ventim-Neves, "RF integrated inductor modeling and its application to optimization-based design", Analog Integrated Circuits and Signal Processing, vol. 73, issue 1: Springer Netherlands, pp. 47-55, 2011. AbstractWebsite

In this paper an optimization-based approach for the design of RF integrated inductors is addressed. For the characterisation of the inductor behaviour the double pi-model is used. The use of this model is twofold. On one hand it enables the generation of the inductor characterisation in a few seconds. On the other hand its integration into the optimization procedure is straightforward. For the evaluation of the model element values analytical expressions based on technology parameters as well as on the device geometric characteristics are used. The use of a technology-based methodology for the evaluation of the model parameters grants the adaptability of the model to any technology. The inductor analytical characterization is integrated into an optimization-based tool for the automatic design of RF integrated inductors. This tool uses a modified genetic algorithm (MGA) optimization procedure, which has proved its validation in previous work. Due to the design parameter constraints nature as well as the topology constraints, discrete variables optimization techniques are used. The accuracy of the results is checked against a non-commercial software.

Pereira, P., A. Sallem, M. Fakhfakh, M. H. Fino, and F. Coito, "A Technology-Aware Optimization of RF Integrated Inductors", Analog Circuits: Applications, Design and Performance: Nova Science Publishers, Inc., pp. 213-234, February, 2012. Abstract

This Chapter presents the optimal design of radio-frequency integrated spiral inductors. The basic idea is to generate an analytical model to characterize integrated inductors based on the double {\ensuremathπ}-model, and offer to the designer an approach to determine the inductor layout parameters. Particle Swarm Optimization technique is used to generate optimal values of parameters of the developed models. Viability of the proposed models is highlighted via comparison with ASITIC simulation results.

Pereira, P., F. Passos, and H. M. Fino, "Optimization-Based Design of RF-VCOs with Tapered Inductors", Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Hershey, PA, USA, IGI Global, pp. 134 - 157, 2015. Abstract

Voltage-Controlled Oscillators (VCOs) are widely used in wireless transceivers. Due to the stringent specifications regarding phase-noise, LC-VCOs are usually adopted. The need for maximizing phase-noise as well as minimizing the power consumption makes imperious the adoption of optimization-based design methodologies. For the optimization of the LC-VCO characteristics, special attention must be paid to the integrated inductor design, since its quality factor may have a strong influence in the LC-VCO phase-noise. Furthermore, designers must ensure that the higher limit of VCO operating frequency is sufficiently below the inductor resonant frequency. In this chapter, a study on the influence of the quality factor of the inductors on the LC-VCO overall behavior is presented. Then, optimization of integrated inductors by exploring the inductor geometric layout is presented. Finally, results obtained for the design of an LC-VCO in 130nm Technology using a previously optimized inductor are presented.

Pereira, P., and M. H. Fino, "CMOS Delay and Power Estimation for Deep Submicrometer Technologies Using EKV Model", 10th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD 2008), pp. 253–257, 2008. Abstract

This paper presents an analytical model for CMOS delay and power estimation in deep sub micrometer technologies. In this paper the EKV transistor model is considered as a way of granting the accuracy of results in the characterization of deep submicron CMOS circuits. The analytical model proposed is valid for a ramp input signal, and takes into account all the operation regions of the transistor as well the influence of the gate-to-drain capacitance. For estimating the power consumption, a simple numerical integration process is applied to the current wave. An application example considering the use of the model for the evaluation of the delay and power consumption associated to a CMOS inverter is considered. The validity of the results obtained with the proposed model for a 1.2V TSMCN65 CMOS inverter is checked against those obtained through Hspice simulation.

Pereira, P., H. Fino, M. Fakhfakh, F. Coito, and M. Ventim-Neves, "LC-VCO Design Challenges in the Nano-Era", Analog/RF and Mixed-Signal Circuit Systematic Design, vol. 233: Springer Berlin Heidelberg, pp. 363-379, 2013. Abstract

The progressive scaling of CMOS technology towards nanometre sizes has made the implementation of highly integrated systems for the wireless communication systems possible. Additionally, higher speed, lower power consumption and area reduction has been reached. Due to the high-density integration needs, as well as to low cost fabrication, RF applications, such as the LC-voltage controlled oscillator (LC-VCO), are usually implemented in CMOS technology. The complexity of designing LC-VCOs has lead to the development of several design methodologies. This chapter introduces an optimization based methodology for the design of LC-VCOs, where its efficiency is granted by the use of analytical models to characterize the active and passive elements’ behaviour.

Pereira, P., and H. Fino, "VCOSYM -an application for the automatic design of ring VCOS", Proc. 12th IEEE Int. Conf. Electronics, Circuits and Systems ICECS 2005, pp. 1–4, 2005. Abstract

This paper presents an application for the automatic design of ring VCOs. In this application a VCO model based on the Npower transistor model is considered as a away of granting the accuracy of results for submicron technologies. In order to easily integrate any VCO previously designed into a PLL automatic design tool, a corresponding linear model of the VCO is automatically generated, yielding a simple and precise characterization for higher level system design. The design of a 150 MHz VCO using a seven stage ring topology is presented. The validity of the design obtained is checked against Hspice simulation of the circuit.

Pereira, P., H. Fino, and M. Ventim-Neves, "LC-VCO design methodology based on evolutionary algorithms", Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on, Seville - Spain, pp. 189 - 192, 2012/sept.. Abstract

In his paper the design of LC-VCOs is addressed. Due to the high-density integration needs as well as to low cost fabrication, RF applications are usually implemented in CMOS technology. However, this technology development brought up several issues such as the degradation of on-chip LC tank quality factor, yielding VCO's phase noise limitation. To overcome phase-noise limitations, optimization design methodologies are usually used. Since electromagnetic simulations are timely expensive, model based approaches are needed. In this work the characterization of the oscillator behaviour is guaranteed by a set of analytical models describing each circuit element performance. A set of working examples for UMC130 technology, aiming the VCO phase noise and power consumption optimization, is addressed. The results presented, spotlight the potential of the proposed design methodology, combined with a GA optimization procedure, for an accurate and timely efficient oscillator design. The accuracy of the results is checked against HSPICE/RF simulator.

Pereira, P., and M. H. Fino, "Delay Propagation of a CMOS Inverter Using the Nexp Transistor Model", XXII Conference on Design of Circuits and Integrated Systems, pp. 12–16, November, 2007. Abstract

This paper presents an analytical model for the delay propagation of a CMOS Invert circuit. In this paper the Nexp transistor model is considered as a way of granting the accuracy of results in the characterization of submicron CMOS circuits. The analytical model proposed is valid for a ramp input, and takes into account all the operation regions of the transistor and take into account the influence of the gate-to-drain capacitance. An application example considering the use of the model for the evaluation of the delay associated to the CMOS inverter is considered. The validity of the results obtained with analytical model of a 1.8V SMIC018 CMOS inverter is checked against Hspice simulation of the circuit.

Pereira, P., M. Kotti, H. Fino, and M. Fakhfakh, "Metaheuristic algorithms comparison for the LC - Voltage controlled oscillators optimal design", 5th International Conference on Modeling, Simulation and Applied Optimization (ICMSAO), Hammamet, Tunisia, pp. 1 - 6, 28-30 April 2013. Abstract

The goal of this paper is to present a comparison among three known metaheuristics: Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Simulated Annealing (SA). For the comparison, the design of an LC - Voltage Controlled Oscillator (LC-VCO) is considered, where the minimization of both VCO phase noise and power consumption is envisaged. The objective of this comparison is to find the algorithm yielding the best solution. The validity of the solution obtained with each metaheuristic algorithm is checked against HSPICE/RF simulation results. Robustness checks for each algorithm are presented at the end of this paper.

Pereira, P., and J. Martins, "Sustainable Heritage Management Towards Mass Tourism Impact: the HERIT-DATA project", 9th International Conference on Intelligent Systems IS’18, Madeira - PT, IEEE, 25-27 Sep., 2018. Abstract

Although tourism is a major engine of economic growth, it also creates a burden hard to manage, and has a great impact on the conservation of the heritage. The HERIT-DATA project aims to reduce the impact of human activities, related to tourism, on cultural heritage, with a special focus on two kind of cultural destinations that can benefit from and be affected by mass tourism: Old towns and places of specific cultural heritage or archaeological interest for visitors, including UNESCO World Heritage Sites. In that framework, HERIT-DATA plans to develop of a sustainable and responsible tourism management towards cultural heritage in MED regions, in particular by taking advantage of technology and innovation in management tools (Smart Cities), as well as other policy and social measures.

Pereira, P., H. Fino, F. Coito, and M. Ventim-Neves, "ADISI- An efficient tool for the automatic design of integrated spiral inductors", Proc. 16th IEEE Int. Conf. Electronics, Circuits, and Systems ICECS 2009, pp. 799–802, 2009. Abstract

This paper introduces a tool for the optimization of CMOS integrated spiral inductors. Its aim is to offer designers a first approach on designing inductors without the need for fabrication. The core of the tool is an optimization procedure where technology constraints on the inductor layout parameters are considered by applying user-defined discretization on the design variables. User-defined constraints between layout parameters may also be accounted for, as a way of taking into account design heuristics. For those cases where the device area is a major concern area minimization may be considered. On the other hand, if a major design goal is the inductor quality factor the tool may yield the layout parameters which maximize the quality factor. The trade-off between quality factor and device area is evaluated through the generation of a graphical representation of quality factor versus output diameter for a given inductance. For the sake of simplicity the pi-model has been used for characterising the inductor. The application was developed in Matlab and the optimization toolbox is used. The validity of the design results obtained is checked against circuit simulation with ASITIC.

Pereira, P., H. Fino, and M. Ventim-Neves, "RF Varactor Design Based on Evolutionary Algorithms", Mixed Design of Integrated Circuits and Systems (MIXDES), 2012 Proceedings of the 19th International Conference, Warsaw, Poland, pp. 277 -282, may, 2012. Abstract

This paper introduces an optimization methodology for the design of RF varactors. The characterization of the varactor behaviour is supported by a set of equations based on technological parameters, granting the accuracy of the results, as well as the adaptability of the model to any technology. The varactor design is achieved through the implementation of a Genetic Algorithms (GA) optimization methodology, which is able to deal with continuous and/or discrete variables, making possible to suit both technological and layout constraints. A set of working examples for UMC130 technology are addressed. The results presented, spotlight the potential of varactor analytical model, combined with a GA optimization procedure, when integrated in optimization design tools. The accuracy of the results is checked against HSPICE simulator.

Pereira, P., S. Valtchev, J. Pina, A. Gonçalves, V. M. Neves, and A. L. Rodrigues, "Power electronics performance in cryogenic environment: evaluation for use in HTS power devices", Journal of Physics: Conference Series, vol. 97, no. 1, pp. 012219, 2008. AbstractWebsite

Power electronics (PE) plays a major role in electrical devices and systems, namely in electromechanical drives, in motor and generator controllers, and in power grids, including high-voltage DC (HVDC) power transmission. PE is also used in devices for the protection against grid disturbances, like voltage sags or power breakdowns. To cope with these disturbances, back-up energy storage devices are used, like uninterruptible power supplies (UPS) and flywheels. Some of these devices may use superconductivity. Commercial PE semiconductor devices (power diodes, power MOSFETs, IGBTs, power Darlington transistors and others) are rarely (or never) experimented for cryogenic temperatures, even when designed for military applications. This means that its integration with HTS power devices is usually done in the hot environment, raising several implementation restrictions. These reasons led to the natural desire of characterising PE under extreme conditions, e. g. at liquid nitrogen temperatures, for use in HTS devices. Some researchers expect that cryogenic temperatures may increase power electronics' performance when compared with room-temperature operation, namely reducing conduction losses and switching time. Also the overall system efficiency may increase due to improved properties of semiconductor materials at low temperatures, reduced losses, and removal of dissipation elements. In this work, steady state operation of commercial PE semiconductors and devices were investigated at liquid nitrogen and room temperatures. Performances in cryogenic and room temperatures are compared. Results help to decide which environment is to be used for different power HTS applications.

Pereira, P., M. H. Fino, and F. V. Coito, "Using discrete-variable optimization for CMOS spiral inductor design", Proc. Int Microelectronics (ICM) Conf, pp. 324–327, 2009. Abstract

In this paper a discrete-variable optimization methodology for the automatic design of CMOS integrated spiral inductors is introduced. The use of discrete variable optimization procedure offers the designer the possibility for exploring the design space exclusively in those points available for the technology under use. Further user-defined constraints between layout parameters may also be incorporated as a way of taking into account design heuristics. A comparison between using discrete-variable optimization and a continuous optimization procedure followed by a discretization of the results is presented, where the benefits of the proposed methodology are presented. An application using the proposed methodology was developed in Matlab and the optimization toolbox is used. For the sake of simplicity the pi-model has been used for characterizing the inductor. The validity of the design results is checked against circuit simulation with ASITIC.