Pedro Pereira
Assistant Professor
Departamento de Engenharia Electrotécnica, Faculdade de Ciências e Tecnologia - Universidade Nova de Lisboa, 2829-516 Caparica, Portugal (email)
CMOS Delay and Power Estimation for Deep Submicrometer Technologies Using EKV Model
- Citation:
- Pereira, P., and M. H. Fino, "CMOS Delay and Power Estimation for Deep Submicrometer Technologies Using EKV Model", 10th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD 2008), pp. 253–257, 2008.
Abstract:
This paper presents an analytical model for CMOS delay and power estimation in deep sub micrometer technologies. In this paper the EKV transistor model is considered as a way of granting the accuracy of results in the characterization of deep submicron CMOS circuits. The analytical model proposed is valid for a ramp input signal, and takes into account all the operation regions of the transistor as well the influence of the gate-to-drain capacitance. For estimating the power consumption, a simple numerical integration process is applied to the current wave. An application example considering the use of the model for the evaluation of the delay and power consumption associated to a CMOS inverter is considered. The validity of the results obtained with the proposed model for a 1.2V TSMCN65 CMOS inverter is checked against those obtained through Hspice simulation.
Notes:
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