Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits

Citation:
Kchaou, B. O., A. Garbaya, M. Kotti, P. Pereira, M. Fakhfakh, and H. M. Fino, "Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits", Integration, the \{VLSI\} Journal, vol. 55, pp. 220 - 226, 2016.

Abstract:

Abstract This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters' variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation \{CMOS\} current conveyor and a \{CMOS\} voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.

Notes:

DOI: 10.1016/j.vlsi.2016.07.001

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