Pedro Pereira

This paper introduces a tool for the optimization of CMOS integrated spiral inductors. Its aim is to offer designers a first approach on designing inductors without the need for fabrication. The core of the tool is an optimization procedure where technology constraints on the inductor layout parameters are considered by applying user-defined discretization on the design variables. User-defined constraints between layout parameters may also be accounted for, as a way of taking into account design heuristics. For those cases where the device area is a major concern area minimization may be considered. On the other hand, if a major design goal is the inductor quality factor the tool may yield the layout parameters which maximize the quality factor. The trade-off between quality factor and device area is evaluated through the generation of a graphical representation of quality factor versus output diameter for a given inductance. For the sake of simplicity the pi-model has been used for characterising the inductor. The application was developed in Matlab and the optimization toolbox is used. The validity of the design results obtained is checked against circuit simulation with ASITIC.

Power Quality is a generic term focusing on several issues, going from reliability to the quality of service provided by the energy supplier. It addresses limiting aspects such as harmonic distortion, flicker, sags, swells and transients... It is important for the students to understand the differences between the large amounts of events that fit into poor power quality category. Moreover it is important for them to analyze real time non-laboratory events. To provide this experience to the students this paper presents a remote m-learning experimental system where several types of poor power quality events can be tested. The developed system is based on a power quality analysis distributed network and can be remotely accessed from a remote computer or smart phones.

Nowadays technologies relate to so many aspects in our daily life that makes society eager for more and more ways of using it. To keep up with this new technological world, all economic sectors, from industry to services, are trying to adapt their products into this new reality. Presently, cultural heritage is already a field where the application of technology allows a static site to be converted into an intelligent environment, with detailed information about a specific monument or historical place, becoming more interesting, not only for local habitants, but also for tourists. This paper describes an application that allows tourists, managers and historical sites' habitants to experience a completely new way of discovering those places, offering a visit with detailed real-time information taking into account their personal interests. Tourists will have at their disposal a full set of optimized routes, combining their interests with their visiting time.

This paper addresses the automatic generation of RF integrated inductors model. In this work the double p-model is used as a way of characterizing the inductor behaviour over a frequency range beyond the self-resonant value. For the evaluation of the model element values analytical expressions based on technology parameters as well as on the device geometric characteristics are used. The use of a technology-based methodology for the evaluation of the model parameters grants the adaptability of the models generated to any technology. The inductor analytical characterization is integrated into an optimization-based tool for the automatic design of RF integrated inductors. This tool uses a Genetic Algorithm (GA) optimization procedure, where user defined constraints on the design parameters are taken into account. Due to the design constraints nature and topology constraints, discrete variables optimization techniques are used.

In this paper we deal with analog active filter design using discrete components taking into consideration tolerance effects. Sensitivity analysis is performed to determine the most influential components in the considered circuit, thus relative higher precision is offered to those parameters. Further, an in-loop optimization technique is considered, thus actual IC models are handled. An application example is presented. HSpice simulation results, supported by Monte Carlo analysis, are given to highlight efficiency of the proposed selection technique.

This paper presents an analytical model for CMOS delay and power estimation in deep sub micrometer technologies. In this paper the EKV transistor model is considered as a way of granting the accuracy of results in the characterization of deep submicron CMOS circuits. The analytical model proposed is valid for a ramp input signal, and takes into account all the operation regions of the transistor as well the influence of the gate-to-drain capacitance. For estimating the power consumption, a simple numerical integration process is applied to the current wave. An application example considering the use of the model for the evaluation of the delay and power consumption associated to a CMOS inverter is considered. The validity of the results obtained with the proposed model for a 1.2V TSMCN65 CMOS inverter is checked against those obtained through Hspice simulation.

This paper presents an analytical model for the delay propagation of a CMOS Invert circuit. In this paper the Nexp transistor model is considered as a way of granting the accuracy of results in the characterization of submicron CMOS circuits. The analytical model proposed is valid for a ramp input, and takes into account all the operation regions of the transistor and take into account the influence of the gate-to-drain capacitance. An application example considering the use of the model for the evaluation of the delay associated to the CMOS inverter is considered. The validity of the results obtained with analytical model of a 1.8V SMIC018 CMOS inverter is checked against Hspice simulation of the circuit.

This paper describes the development of an open source system for monitoring and data acquisition of several energy analyzers. The developed system is based on a computer with Internet/Intranet connection by means of RS485 using Modbus RTU as communication protocol. The monitoring/metering system was developed for large building complexes and was validated in the Faculdade de Ciências e Tecnologia University campus. The system considers two distinct applications. The first one allows the user to verify, in real time, the energy consumption of any department in the complex, produce load diagrams, tables and print, email or save all available data. The second application keeps records of active/reactive energy consumption in order to verify the existence of some anomalous situation, and also monthly charge energy consumption to each corresponding department.

Swarm intelligence techniques are among the most talented and successful approaches that gained a lot of popularity over the past two decades. They are inspired by animal behavior (such as ants, termites and bees) and insect conduct (by swarm, herd, flock and shoal phenomena) in order to develop these techniques in terms of mimicking their problem/solution abilities. These techniques provide good approximate solutions in a reasonable time for solving hard and complex problems in many engineering fields. This book is intended for researchers, engineers and graduate students with interests in swarm intelligence algorithms and their applications. It discusses and describes the various swarm intelligence techniques as useful tools for solving practical problems, such as urban traffic optimization, electrical engineering problems and the design of integrated analog circuits.

This work introduces a tool for the optimization of CMOS integrated spiral inductors. The main objective of this tool is to offer designers a first approach for the determination of the inductor layout parameters. The core of the tool is a Genetic Algorithm (GA) optimization procedure where technology constraints on the inductor layout parameters are considered. Further constraints regarding inductor design heuristics are also accounted for. Since the layout parameters are inherently discrete due to technology and topology constraints, discrete variable optimization techniques are used. The Matlab GA toolbox is used and the modifications on the GA functions, yielding technology feasible solutions is presented. For the sake of efficiency and simplicity the pi-model is used for characterizing the inductor. The validity of the design results obtained with the tool, is checked against circuit simulation with ASITIC.

Abstract This paper proposes a hybrid methodology for the evaluation of integrated inductors sensitivity against technological/geometrical parameters variation. The obtained results are used in an optimization-based design environment for integrated inductors, as a way of guaranteeing that obtained solutions are robust against parameter variation. For the inductor characterization, a lumped element model is used, where each element value is evaluated through physics based equations. The sensitivity of the inductor characterization to parameter variations is evaluated at two levels. At the physical level, the sensitivity of the model element values to technological/geometrical parameters variations is computed through an equation-based strategy. Then, the sensitivity of the inductor characterization to the model parameter variations is obtained through a simulation-based approach, where the Richardson extrapolation technique is used for the calculation of the partial derivatives. Several examples considering the evaluation of sensitivity of both inductance and quality factor of two inductors in \{UMC130\} technology are presented. Obtained results are compared against Monte-Carlo simulations.

In this paper an interoperability solution is proposed, aiming to go from (building) construction models to energy simulation. Moreover, the energy simulation results will feed the KPI’s analysis of a designed building. The proposed solution will be used to translate different data formats allowing the communication between different systems in an automated environment. The solution presented in this paper exploits the concept of Plug’n’Interoperate (PnI), that is supported by the principle of self-configuration as to automate, as much as possible, the configuration and participation of systems into a shared interoperability environment. In order to validate this approach two different scenarios were taken into account, translating from a CAD (Computer- Aided Design) model data format to an energy simulation data format.

The progressive scaling of CMOS technology towards nanometre sizes has made the implementation of highly integrated systems for the wireless communication systems possible. Additionally, higher speed, lower power consumption and area reduction has been reached. Due to the high-density integration needs, as well as to low cost fabrication, RF applications, such as the LC-voltage controlled oscillator (LC-VCO), are usually implemented in CMOS technology. The complexity of designing LC-VCOs has lead to the development of several design methodologies. This chapter introduces an optimization based methodology for the design of LC-VCOs, where its efficiency is granted by the use of analytical models to characterize the active and passive elements’ behaviour.

In his paper the design of LC-VCOs is addressed. Due to the high-density integration needs as well as to low cost fabrication, RF applications are usually implemented in CMOS technology. However, this technology development brought up several issues such as the degradation of on-chip LC tank quality factor, yielding VCO's phase noise limitation. To overcome phase-noise limitations, optimization design methodologies are usually used. Since electromagnetic simulations are timely expensive, model based approaches are needed. In this work the characterization of the oscillator behaviour is guaranteed by a set of analytical models describing each circuit element performance. A set of working examples for UMC130 technology, aiming the VCO phase noise and power consumption optimization, is addressed. The results presented, spotlight the potential of the proposed design methodology, combined with a GA optimization procedure, for an accurate and timely efficient oscillator design. The accuracy of the results is checked against HSPICE/RF simulator.

The goal of this paper is to present a comparison among three known metaheuristics: Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Simulated Annealing (SA). For the comparison, the design of an LC - Voltage Controlled Oscillator (LC-VCO) is considered, where the minimization of both VCO phase noise and power consumption is envisaged. The objective of this comparison is to find the algorithm yielding the best solution. The validity of the solution obtained with each metaheuristic algorithm is checked against HSPICE/RF simulation results. Robustness checks for each algorithm are presented at the end of this paper.

Inductive superconducting fault current limiters have already demonstrated their technical viability in electrical networks. Its architecture and robustness make them potentially adequate for distribution networks, and this type of devices is considered as an enabling technology for the advent of embedded generation with renewable energy sources. In order to promote the growth and maturity of these superconducting technologies, fast design tools must be developed, allowing simulating devices with different materials in grids with diverse characteristics. This work presents advances in the development of such tool, which, at present stage, is an effective alternative to software simulations by finite elements methods, reducing dramatically computation time. The algorithms are now compared with experimental results from a laboratory scale prototype, showing the need to refine them.

This work deals with the multi-objective optimization of analog circuits by generating the Pareto front where elements are low sensitive to parameters' variations. NSGA-II is used for obtaining the non-dominated solutions. Richardson extrapolation technique is used for the in-loop optimization approach for computing partial derivatives and, thus, the solutions' sensitivity. NSGA-II Pareto fronts' intrinsic ranking is exploited for the generation of the new ‘low-sensitive’ Pareto front. The case of the optimal sizing of a CMOS voltage follower is considered to exemplify the proposed approach.

The continuing size reduction of electronic devices imposes design challenges to optimize the performances of modern electronic systems, such as: wireless services, telecom and mobile computing. Fortunately, those design challenges can be overcome thanks to the development of Electronic Design Automation (EDA) tools. In the analog, mixed signal and radio-frequency (AMS/RF) domains, circuit optimization tools have demonstrated their usefulness in addressing design problems taking into account downscaling technological aspects. Recent advances in EDA have shown that the simulation-based sizing technique is a very interesting solution to the ‘complex’ modelling task in the circuit design optimization problem. In this paper we propose a multi-objective simulation-based optimization tool. A CMOS LC-VCO circuit is presented to show the viability of this tool. The tool is used to generate the Pareto front linking two conflicting objectives, namely the VCO Phase Noise and Power Consumption. The accuracy of the results is checked against HSPICE/RF simulations.

The study and assessment of Power Quality issues is nowadays a very important subject, particularly regarding Cyber-physical and Industrial Agents based systems, which are extremely sensitive to Power Quality disturbances. Giving students or engineers practical experience in this field requires a large investment from teaching institutions. This paper presents a laboratory device that emulates Power Quality disturbances in order to provide the required experimental expertize in the subject. It addresses limiting aspects such as harmonic distortion, flicker, sags, swells and transients. The developed system presents a good opportunity for technicians, even without deep knowledge on the field of power quality, to learn basic principles and be able to identify Power Quality events. Since the system is based on real data, represents a valuable approach giving trainees practical knowledge on the field.

The need for implementing low cost, fully integrated RF wireless transceivers has motivated the widespread use CMOS technology. However, in the particular case for voltage-controlled oscillators (VCO) where ever more stringent specifications in terms of phase-noise must be attained, the design of the on-chip LC tank is a challenging task, where fully advantage of the actual technologies characteristics must be pushed to nearly its limits. To overcome phase-noise limitations arising from the low quality factor of integrated inductors, optimization design methodologies are usually used. In this paper a model-based optimization approach is proposed. In this work the characterization of the oscillator behaviour is guaranteed by a set of analytical models describing each circuit element performance. A set of working examples for UMC130 technology, aiming the minimization of both VCO phase noise and power consumption, is addressed. The results presented, illustrate the potential of a GA optimization procedure design methodology yielding accurate and timely efficient oscillator designs. The validity of the results is checked against HSPICE/RF simulations.

This paper introduces a variability-aware methodology for the design of LC-VCOs in Nano-CMOS technologies. The complexity of the design as well as the necessity for having an environment offering the possibility for exploring design trade-offs has led to the development of design methodologies based multi-objective optimization procedures yielding the generation of Pareto-optimal surfaces. The efficiency of the process is granted by using analytical models for both passive and active devices. Although physics-based analytical expressions have been proposed for the evaluation of the lumped elements, the variability of the process parameters is usually ignored due to the difficulty to formalize it into an optimization performance index. The usually adopted methodology of considering only optimum solutions for the Pareto surface, may lead to pruning quasi-optimal solutions that may prove to be better, should their sensitivity to process parameter variation be accounted for. In this work we propose starting by generating an extended Pareto surface where both optimum and quasi-optimum solutions are considered. Finally information on the sensitivity to process parameter variations, is used for electing the best design solution.

Voltage-Controlled Oscillators (VCOs) are widely used in wireless transceivers. Due to the stringent specifications regarding phase-noise, LC-VCOs are usually adopted. The need for maximizing phase-noise as well as minimizing the power consumption makes imperious the adoption of optimization-based design methodologies. For the optimization of the LC-VCO characteristics, special attention must be paid to the integrated inductor design, since its quality factor may have a strong influence in the LC-VCO phase-noise. Furthermore, designers must ensure that the higher limit of VCO operating frequency is sufficiently below the inductor resonant frequency. In this chapter, a study on the influence of the quality factor of the inductors on the LC-VCO overall behavior is presented. Then, optimization of integrated inductors by exploring the inductor geometric layout is presented. Finally, results obtained for the design of an LC-VCO in 130nm Technology using a previously optimized inductor are presented.

Power electronics (PE) plays a major role in electrical devices and systems, namely in electromechanical drives, in motor and generator controllers, and in power grids, including high-voltage DC (HVDC) power transmission. PE is also used in devices for the protection against grid disturbances, like voltage sags or power breakdowns. To cope with these disturbances, back-up energy storage devices are used, like uninterruptible power supplies (UPS) and flywheels. Some of these devices may use superconductivity. Commercial PE semiconductor devices (power diodes, power MOSFETs, IGBTs, power Darlington transistors and others) are rarely (or never) experimented for cryogenic temperatures, even when designed for military applications. This means that its integration with HTS power devices is usually done in the hot environment, raising several implementation restrictions. These reasons led to the natural desire of characterising PE under extreme conditions, e. g. at liquid nitrogen temperatures, for use in HTS devices. Some researchers expect that cryogenic temperatures may increase power electronics' performance when compared with room-temperature operation, namely reducing conduction losses and switching time. Also the overall system efficiency may increase due to improved properties of semiconductor materials at low temperatures, reduced losses, and removal of dissipation elements. In this work, steady state operation of commercial PE semiconductors and devices were investigated at liquid nitrogen and room temperatures. Performances in cryogenic and room temperatures are compared. Results help to decide which environment is to be used for different power HTS applications.

This paper presents a remote laboratory linked with mobile devices for real data analysis on the field of power quality. A global system was developed from the power quality analyzer into the human machine interface devoted to the m-learning system. This m-learning system is intended to be used in a long life learning perspective. The developed remote laboratory is a good opportunity for people, even without deep knowledge on the field, to learn power quality principles in an applied way. Since the system is based on real data, is a good approach to give trainees practical knowledge on the field.