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Conference Paper
Vale, T. M., R. J. Dias, and J. M. Lourenço, "Uma Infraestrutura para Suporte de Memória Transacional Distribuída", INForum 2012: Proceedings of INForum Simpósio de Informática, Monte de Capraica, PT, Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa, 7 Sep., 2012. Abstractinforum-dstm.pdf

As técnicas e algoritmos desenvolvidos sobre diferentes infraestruturas específicas dificilmente podem ser comparados entre si. Este princípio também se aplica às infraestruturas para execução de Memória Transacional Distribuída (MTD), pois não só são muito escassas aquelas que permitem o desenvolvimento, teste e comparação de vários algoritmos e técnicas de implementação, como fornecem uma interface intrusiva para o programador. Sem uma comparação justa, não é possível aferir quais as técnicas e algoritmos mais apropriados em cada contexto de utilização (workload). Neste artigo propomos uma infraestrutura generalista, muito flexível, que possibilita a experimentação de várias estratégias de MTD, permitindo o desenvolvimento de uma grande variedade de algoritmos e de técnicas de implementação eficientes e otimizadas. Através da sua utilização, é agora possível a comparação de técnicas e algoritmos em diferentes contextos de utilização (workloads), recorrendo a uma única infraestrutura e com implicações mínimas no código da aplicação.

Lourenço, J. M., R. J. Dias, J. Luís, M. Rebelo, and V. Pessanha, "Understanding the Behavior of Transactional Memory Applications", Proceedings of the 7th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging (PADTAD'09), New York, NY, USA, ACM, pp. 31–39, 2009. Abstractpadtad2009.pdf

Transactional memory is a new trend in concurrency control that was boosted by the advent of multi-core processors and the near to come many-core processors. It promises the performance of finer grain with the simplicity of coarse grain threading. However, there is a clear absence of software development tools oriented to the transactional memory programming model, which is confirmed by the very small number of related scientific works published until now. This paper describes ongoing work. We propose a very low overhead monitoring framework, developed specifically for monitoring TM computations, that collects the transactional events into a single log file, sorted in a global order. This framework is then used by a visualization tool to display different types of charts from two categories: statistical charts and thread-time space diagrams. These last diagrams are interactive, allowing to identify conflicting transactions. We use the visualization tool to analyse the behavior of two different, but similar, testing applications, illustrating how it can be used to better understand the behavior of these transactional memory applications.

Dias, R. J., and J. M. Lourenço, "Unifying Memory and Database Transactions", Proceedings of the 15th International Euro-Par Conference on Parallel Processing, Berlin, Heidelberg, Springer-Verlag, pp. 349–360, 2009. Abstracteuropar2009-umadt.pdf

Software Transactional Memory is a concurrency control technique gaining increasing popularity, as it provides high-level concurrency control constructs and eases the development of highly multi-threaded applications. But this easiness comes at the expense of restricting the operations that can be executed within a memory transaction, and operations such as terminal and file I/O are either not allowed or incur in serious performance penalties. Database I/O is another example of operations that usually are not allowed within a memory transaction. This paper proposes to combine memory and database transactions in a single unified model, benefiting from the ACID properties of the database transactions and from the speed of main memory data processing. The new unified model covers, without differentiating, both memory and database operations. Thus, the users are allowed to freely intertwine memory and database accesses within the same transaction, knowing that the memory and database contents will always remain consistent and that the transaction will atomically abort or commit the operations in both memory and database. This approach allows to increase the granularity of the in-memory atomic actions and hence, simplifies the reasoning about them.

Farchi, E., I. Segall, J. M. Lourenço, and D. Sousa, "Using Program Closures to Make an Application Programming Interface (API) Implementation Thread Safe", PADTAD'12: Proceedings of the 10th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging, Minneapolis, MN, USA, ACM, 2012. Abstractprogramclosure.pdf

A set of methods defining an API (Application Programming Interface) are to be made thread safe; thus running any subset of these methods in parallel should not create races or deadlocks. Originally, the set of methods were not designed to be thread safe, so races and deadlocks are expected when running them in parallel. The number of possible interleavings when running methods from this API in parallel is huge, and this work focuses on the identification of the high level data races introduced by such interleavings. We propose an analysis that avoids the exhaustive exploration of all possible interleavings. For a concurrent program P, the closure of P, clos(P), is defined. Roughly speaking, we can say that the clos(P) is obtained by adding threads to P in such a way that high level data races resulting from running P in parallel to other programs are exposed statically. A set of methods representing the API is then modeled as a set of concurrent programs and their closure is analysed to identify high level data races. These high level data races are then inspected and removed to make the API thread safe. We illustrate the application of this methodology with a simple use case.

Dias, R. J., D. Distefano, J. C. Seco, and J. M. Lourenço, "Verification of Snapshot Isolation in Transactional Memory Java Programs", Proceedings of the 26th European Conference on Object-Oriented Programming, Beijing, China, 11-16 June, 2012. Abstractecoop12.pdf

This paper presents an automatic verification technique for transactional memory Java programs executing under snapshot isolation level. We certify which transactions in a program are safe to execute under snapshot isolation without triggering the write-skew anomaly, opening the way to run-time optimizations that may lead to considerable performance enhancements. Our work builds on a novel deep-heap analysis technique based on separation logic to statically approximate the read- and write-sets of a transactional memory Java program. We implement our technique and apply our tool to a set of micro benchmarks and also to one benchmark of the STAMP package. We corroborate known results, certifying some of the examples for safe execution under snapshot isolation by proving the absence of write-skew anomalies. In other cases our analysis has identified transactions that potentially trigger previously unknown write-skew anomalies.>

Conference Proceedings
Eder, K., J. M. Lourenço, and O. Shehory, "Hardware and Software: Verification and Testing", Haifa Verification Conference, Haifa, Israel, Springer Berlin / Heidelberg, 2011. Abstract

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Lourenço, J. M., and E. Farchi, "Multicore Software Engineering, Performance, and Tools", Proceedings of the 2nd International Conference on Multicore Software Engineering, Performance, and Tools, MUSEPAT 2013, Saint Petersburg, Russia, August 19–20, 2013, vol. 8063: Springer Berlin Heidelberg, 2013. Abstract

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Lourenço, J. M., N. Preguiça, R. J. Dias, J. N. Silva, J. Garcia, and L. Veiga, "NGenVM: New Generation Execution Environments", EuroSys, Nuremberg, Germany, 2009. Abstractngenvm-poster.pdf

This document describes a work-in-progress development of NGen-VM, a distributed infrastructure that manages execution environments with run-time and programming language support targeting applications developed in the Java programming language, deployed over clusters of many-core computers. For each running application or suite of related applications, a dedicated single-system image will be provided, regardless of the concurrent threads running on a single machine (on several cores) or scattered on different computers. Such system images rely on a single model for concurrency management (Transactional Shared Memory Model), in order fill the gap between the hardware infrastructure of clusters of many-core nodes and the application runtime that is independent from that hardware infrastructure. Interactions between threads in the same tasks will be supported by a Transactional Memory framework that provides the programming language with Atomic and Isolated code regions. Interactions between thread on different machines will also use the Transactional Memory model, but now resorting to a Distributed Shared Memory abstraction.

Cunha, J. C., W. Fleischman, J. M. Lourenço, and V. K. Proulx, Proceedings of the 10th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education (ITiCSE'05), , New York, NY, USA, ACM, 2005. Abstract

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Journal Article
Lourenço, J. M., J. C. Cunha, and V. Moreira, "Control and Debugging of Distributed Programs Using Fiddle", CoRR, vol. cs.DC/0309049, pp. 143–157, 2003. Abstractaadebug.pdfWebsite

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Lourenço, J., D. Sousa, B. C. Teixeira, and R. J. Dias, "Detecting concurrency anomalies in transactional memory programs", Comput. Sci. Inf. Syst., vol. 8, issue 2, no. 2, pp. 533–548, 2011. Abstractcomsis-2011.pdf

Software transactional memory is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to main memory (RAM). This paper discusses how to support revertible operations, such as memory allocation and release, within software libraries that will be used in software memory transactional contexts. The proposal is based in the extension of the transaction life cycle state diagram with new states associated to the execution of user-defined handlers. The proposed approach is evaluated in terms of functionality and performance by way of a use case study and performance tests. Results demonstrate that the proposal and its current implementation are flexible, generic and efficient

Dias, R. J., J. M. Lourenço, and G. Cunha, "Developing libraries using software transactional memory", Comput. Sci. Inf. Syst., vol. 5, issue 2, no. 2, pp. 103–117, 2008. Abstractcomsis_final.pdf

Software transactional memory is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to main memory (RAM). This paper discusses how to support revertible operations, such as memory allocation and release, within software libraries that will be used in software memory transactional contexts. The proposal is based in the extension of the transaction life cycle state diagram with new states associated to the execution of user-defined handlers. The proposed approach is evaluated in terms of functionality and performance by way of a use case study and performance tests. Results demonstrate that the proposal and its current implementation are flexible, generic and efficient

Dias, R. J., T. M. Vale, and J. M. Lourenço, "Efficient support for in-place metadata in Java software transactional memory", Concurrency and Computation: Practice and Experience, vol. 25, no. 17, pp. 2394–2411, 2013. Abstractccpe2013-dias.pdfWebsite

Software transactional memory (STM) algorithms associate metadata with the memory locations accessed during a transaction's lifetime. This metadata may be stored in an external table by resorting to a mapping function that associates the address of a memory cell with the table entry containing the corresponding metadata (out-place or external strategy). Alternatively, the metadata may be stored adjacent to the associated memory cell by wrapping the cell and metadata together (in-place strategy). The implementation techniques to support these two approaches are very different and each STM framework is usually biased towards one of them, only allowing the efficient implementation of STM algorithms which suit one of the approaches and inhibiting a fair comparison with STM algorithms suiting the other. In this paper, we introduce a technique to implement in-place metadata that does not wrap memory cells, thus overcoming the bias and allowing STM algorithms to directly access the transactional metadata. The proposed technique is available as an extension to Deuce and enables the efficient implementation of a wide range of STM algorithms and their fair (unbiased) comparison in a common STM framework. We illustrate the benefits of our approach by analyzing its impact in two popular transactional memory algorithms with several transactional workloads, TL2 and multiversioning, each befitting out-place and in-place, respectively.

Cunha, J. C., J. M. Lourenço, and T. Antão, "An experiment in tool integration: the {DDBG} parallel and distributed debugger", J. Syst. Archit., vol. 45, New York, NY, USA, Elsevier North-Holland, Inc., pp. 897–907, may, 1999. Abstractjsa99.pdfWebsite

Most known teaching experiences focus on parallel computing courses only, but some teaching experiences on distributed computing courses have also been reported. In this paper we describe a course on Parallel and Distributed Processing that is taught at undergraduate level in the Computer Science degree of our University.This course presents an integrated approach concerning concurrency, parallelism, and distribution issues. It's a breadth-first course addressing a wide spectrum of abstractions: the theoretical component focus on the fundamental abstractions to model concurrent systems, including process cooperation schemes, concurrent programming models, data and control distribution, concurrency control and recovery in transactional systems, and parallel processing models; the practical component illustrates the design and implementation issues involved in selected topics such as a data and control distribution problem, a distributed transaction-based support system and a parallel algorithm.We also discuss how this approach has been contributing to prepare the student to further actions regarding research and development of concurrent, distributed, or parallel systems.

Kacsuk, P., J. C. Cunha, G. Dózsa, J. M. Lourenço, T. Fadgyas, and T. Antão, "A graphical development and debugging environment for parallel programs", Parallel Comput., vol. 22, Amsterdam, The Netherlands, The Netherlands, Elsevier Science Publishers B. V., pp. 1747–1770, 1997. Abstractpar-comp97.pdfWebsite

To provide high-level graphical support for PVM (Parallel Virtual Machine) based program development, a complex programming environment (GRADE) is being developed. GRADE currently provides tools to construct, execute, debug, monitor and visualise message-passing parallel programs. It offers high-level graphical programming abstraction mechanism to construct parallel applications by introducing a new graphical language called GRAPNEL. GRADE also provides the programmer with the same graphical user interface during the program design and debugging stages. A distributed debugging engine (DDBG) assists the user in debugging GRAPNEL programs on distributed memory computer architectures. Tape/PVM and PROVE support the performance monitoring and visualization of parallel programs developed in the GRADE environment.

Cunha, J. C., and J. M. Lourenço, "An Integrated Course on Parallel and Distributed Processing", SIGCSE Bull., vol. 30, New York, NY, USA, ACM, pp. 217–221, 1998. Abstractsigcse98.pdfWebsite

Most known teaching experiences focus on parallel computing courses only, but some teaching experiences on distributed computing courses have also been reported. In this paper we describe a course on Parallel and Distributed Processing that is taught at undergraduate level in the Computer Science degree of our University.This course presents an integrated approach concerning concurrency, parallelism, and distribution issues. It's a breadth-first course addressing a wide spectrum of abstractions: the theoretical component focus on the fundamental abstractions to model concurrent systems, including process cooperation schemes, concurrent programming models, data and control distribution, concurrency control and recovery in transactional systems, and parallel processing models; the practical component illustrates the design and implementation issues involved in selected topics such as a data and control distribution problem, a distributed transaction-based support system and a parallel algorithm.We also discuss how this approach has been contributing to prepare the student to further actions regarding research and development of concurrent, distributed, or parallel systems.

Lourenço, J. M., J. C. Cunha, H. Krawczyk, P. Kuzora, M. Neyman, and B. Wiszniewski, "An integrated testing and debugging environment for parallel and distributed programs", EUROMICRO Conference, Los Alamitos, CA, USA, IEEE Computer Society, pp. 291, 1997. Abstracteuromicro97.pdfWebsite

To achieve a certain degree of confidence that a given program follows its specification, a testing phase must be included in the program development process, and also a complementary debugging phase to help locating the program's bugs. This paper presents an environment which results of the composition and integration of two basic tools: STEPS (Structural TEsting of Parallel Software), which is a testing tool, and DDBG (Distributed DeBuGger), which is a debugging tool. The two tools are presented individually as stand-alone tools, and we describe how they were combined through the use of another intermediate tool: DEIPA (Deterministic re-Execution and Interactive Program Analysis). We claim that the result achieved is a very effective testing and debugging environment.

Sousa, D. G., R. J. Dias, C. Ferreira, and J. M. Lourenço, "Preventing Atomicity Violations with Contracts", ArXiv e-prints, 2015. Abstract1505.02951v1-dsousa.pdfWebsite

Software developers are expected to protect concurrent accesses to shared regions of memory with some mutual exclusion primitive that ensures atomicity properties to a sequence of program statements. This approach prevents data races but may fail to provide all necessary correctness properties.The composition of correlated atomic operations without further synchronization may cause atomicity violations. Atomic violations may be avoided by grouping the correlated atomic regions in a single larger atomic scope. Concurrent programs are particularly prone to atomicity violations when they use services provided by third party packages or modules, since the programmer may fail to identify which services are correlated. In this paper we propose to use contracts for concurrency, where the developer of a module writes a set of contract terms that specify which methods are correlated and must be executed in the same atomic scope. These contracts are then used to verify the correctness of the main program with respect to the usage of the module(s). If a contract is well defined and complete, and the main program respects it, then the program is safe from atomicity violations with respect to that module. We also propose a static analysis based methodology to verify contracts for concurrency that we applied to some real-world software packages. The bug we found in Tomcat 6.0 was immediately acknowledged and corrected by its development team.

Farchi, E., R. M. Hierons, and J. M. Lourenço, "Special issue on Testing, Analysis and Debugging of Concurrent Programs", Software Testing, Verification and Reliability, vol. 25, no. 3, pp. 165–166, May, 2015. AbstractWebsite

This special issue concerns a range of issues related to the development of concurrent programs. This is an important topic, because many systems are now either multi-threaded or distributed, and it is well known that concurrency makes testing, analysis and debugging significantly more complicated. Essentially, the alternative interleavings of events can lead to different behaviours, and so any analysis, debugging or testing technique must consider these interleavings. The interest in this topic is reflected in the larger than normal issue, which contains five papers. The papers fall into three groups: we start with a paper on debugging, then have two on static analysis techniques and finally have two on testing. All papers were reviewed in the normal way.

Duarte Vitor, Lourenço João M., C. J. C., "Supporting On-line Distributed Monitoring and Debugging", Parallel and Distributed Computing Practices, vol. 4, no. 3, pp. 43–59, 2001. Abstractpdcp.pdfWebsite

Monitoring systems have traditionally been developed with rigid objectives and functionalities, and tied to specific languages, libraries and run-time environments. There is a need for more flexible monitoring systems which can be easily adapted to distinct requirements. On-line monitoring has been considered as increasingly important for observation and control of a distributed application. In this paper we discuss monitoring interfaces and architectures which support more extensible monitoring and control services. We describe our work on the development of a distributed monitoring infrastructure, and illustrate how it eases the implementation of a complex distributed debugging architecture. We also discuss several issues concerning support for tool interoperability and illustrate how the cooperation among multiple concurrent tools can ease the task of distributed debugging.

Kwiatkowski, J., M. Andruszkiewicz, E. Luque, T. Margalef, J. C. Cunha, J. M. Lourenço, H. Krawczyk, and S. Szejko, "Teaching parallel processing: development of curriculum and software tools", SIGCUE Outlook, vol. 24, New York, NY, USA, ACM, pp. 159–161, 1996. Abstractsigcse96.pdfWebsite

This paper presents an approach to education in Parallel and Distributed Processing undertaken in the Technical University of Gdansk and Technical University of Wroclaw. The paper gives a detailed structure of the project entitled "Teaching Parallel Processing: Development of Curriculum and Software Tools" which was started in 1994 and will be finish in 1997. Two universities from Poland: Technical University of Gdansk and Technical University of Wroclaw and two universities from EC countries: University Autònoma of Barcelona from Spain and University Nova of Lisbon from Portugal participate in the presented project. The main aim of the project is to develop existing curricula of Computer Science specialisation and to establish specialisation concerned with parallel and distributed processing at Polish universities.

Cunha, J. C., J. Lourenço, and V. Duarte, "Using DDBG to Support Testing and High-level Debugging Interfaces", Computers and Artificial Intelligence, vol. 17, no. 5, 1998. Abstractcaij98.pdfWebsite

This paper describes our experience with the design and implementation of a distributed debugger for C/PVM programs within the scope of the SEPP and HPCTI Copernicus projects. These projects aimed at the development of an integrated parallel software engineering environment based on a high-level graphical parallel programming model (GRAPNEL) and a set of associated tools supporting graphical edition, compilation, simulated and real parallel execution, testing, debugging, performance monitoring, mapping, and load balancing. We discuss how the development of the debugging tool was strongly influenced by the requirements posed by other tools in the environment, namely support for high-level graphical debugging of GRAPNEL programs, and support for the integration of static and dynamic analysis tools. We describe the functionalities of the DDBG debugger and its internal architecture, and discuss its integration with two separate tools in the SEPP/HPCTI environment: the GRED graphical editor for GRAPNEL programs, and the STEPS testing tool for C/PVM programs.

Miscellaneous
Dias, R. J., J. M. Lourenço, and J. C. Seco, Detection of Snapshot Isolation Anomalies in Software Transactional Memory: A Statical Analysis Approach, , no. UNL-DI-5-2011: Departamento de Informática FCT/UNL, 2011. Abstract

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