@article {Kchaou2016220,
	title = {Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits},
	journal = {Integration, the \{VLSI\} Journal},
	volume = {55},
	year = {2016},
	note = {<p>DOI: 10.1016/j.vlsi.2016.07.001</p>
},
	pages = {220 - 226},
	abstract = {<p>Abstract This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters{\textquoteright} variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation \{CMOS\} current conveyor and a \{CMOS\} voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.</p>
},
	keywords = {Richardson extrapolation technique},
	issn = {0167-9260},
	doi = {http://dx.doi.org/10.1016/j.vlsi.2016.07.001},
	url = {https://doi.org/10.1016/j.vlsi.2016.07.001},
	author = {O. Bellaaj Kchaou and A. Garbaya and Kotti, M. and P Pereira and Fakhfakh, M. and M. Helena Fino}
}
