<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">O. Bellaaj Kchaou</style></author><author><style face="normal" font="default" size="100%">A. Garbaya</style></author><author><style face="normal" font="default" size="100%">Kotti, M.</style></author><author><style face="normal" font="default" size="100%">P Pereira</style></author><author><style face="normal" font="default" size="100%">Fakhfakh, M.</style></author><author><style face="normal" font="default" size="100%">M. Helena Fino</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits</style></title><secondary-title><style face="normal" font="default" size="100%">Integration, the \{VLSI\} Journal</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">Richardson extrapolation technique</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2016</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://doi.org/10.1016/j.vlsi.2016.07.001</style></url></web-urls></urls><volume><style face="normal" font="default" size="100%">55</style></volume><pages><style face="normal" font="default" size="100%">220 - 226</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">&lt;p&gt;Abstract This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters' variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation \{CMOS\} current conveyor and a \{CMOS\} voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.&lt;/p&gt;
</style></abstract><notes><style face="normal" font="default" size="100%">&lt;p&gt;DOI: 10.1016/j.vlsi.2016.07.001&lt;/p&gt;
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