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2016
Kchaou, B. O., A. Garbaya, M. Kotti, P. Pereira, M. Fakhfakh, and H. M. Fino, "Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits", Integration, the \{VLSI\} Journal, vol. 55, pp. 220 - 226, 2016. AbstractWebsite

Abstract This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters' variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation \{CMOS\} current conveyor and a \{CMOS\} voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.

2013
Sallem, A., P. Pereira, M. Fakhfakh, and H. Fino, "A Multi-objective Simulation Based Tool: Application to the Design of High Performance LC-VCOs", Technological Innovation for the Internet of Things, vol. 394, Portugal, Springer Berlin Heidelberg, pp. 459-468, 2013. Abstract

The continuing size reduction of electronic devices imposes design challenges to optimize the performances of modern electronic systems, such as: wireless services, telecom and mobile computing. Fortunately, those design challenges can be overcome thanks to the development of Electronic Design Automation (EDA) tools. In the analog, mixed signal and radio-frequency (AMS/RF) domains, circuit optimization tools have demonstrated their usefulness in addressing design problems taking into account downscaling technological aspects. Recent advances in EDA have shown that the simulation-based sizing technique is a very interesting solution to the ‘complex’ modelling task in the circuit design optimization problem. In this paper we propose a multi-objective simulation-based optimization tool. A CMOS LC-VCO circuit is presented to show the viability of this tool. The tool is used to generate the Pareto front linking two conflicting objectives, namely the VCO Phase Noise and Power Consumption. The accuracy of the results is checked against HSPICE/RF simulations.

Almeida, P., P. Pereira, and H. Fino, "Using Variable Width RF Integrated Inductors for Quality Factor Optimization", Technological Innovation for the Internet of Things, vol. 394: Springer Berlin Heidelberg, pp. 619-627, 2013. Abstract

The advancement of CMOS technology led to the integration of more complex functions. In the particular of wireless transceivers, integrated LC tanks are becoming popular both for VCOs and integrated filters [1]. For RF applications the main challenge is still the design of integrated inductors with the maximum quality factor. For that purpose, tapered, i.e., variable width inductors have been proposed in the literature. In this paper, analytical expressions for the determination the pi-model parameters, for the characterization of variable width integrated inductors are proposed. The expressions rely exclusively on geometrical and technological parameters, thus granting the rapid adaptation of the model to different technologies. The results obtained with the model are compared against simulation with ASITIC, showing errors below 10%. The model is then integrated into an optimization procedure where inductors with a quality factor improvement in the order of 20-30% are obtained, when compared with fixed width inductors.

2010
Jorge, A., J. Guerreiro, P. Pereira, J. Martins, and L. Gomes, "Energy Consumption Monitoring System for Large Complexes", Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2010, vol. 314, Costa de Caparica - Portugal, Springer Boston, pp. 419-426, 2010. Abstract

This paper describes the development of an open source system for monitoring and data acquisition of several energy analyzers. The developed system is based on a computer with Internet/Intranet connection by means of RS485 using Modbus RTU as communication protocol. The monitoring/metering system was developed for large building complexes and was validated in the Faculdade de Ciências e Tecnologia University campus. The system considers two distinct applications. The first one allows the user to verify, in real time, the energy consumption of any department in the complex, produce load diagrams, tables and print, email or save all available data. The second application keeps records of active/reactive energy consumption in order to verify the existence of some anomalous situation, and also monthly charge energy consumption to each corresponding department.

2008
Pereira, P., S. Valtchev, J. Pina, A. Gonçalves, V. M. Neves, and A. L. Rodrigues, "Power electronics performance in cryogenic environment: evaluation for use in HTS power devices", Journal of Physics: Conference Series, vol. 97, no. 1, pp. 012219, 2008. AbstractWebsite

Power electronics (PE) plays a major role in electrical devices and systems, namely in electromechanical drives, in motor and generator controllers, and in power grids, including high-voltage DC (HVDC) power transmission. PE is also used in devices for the protection against grid disturbances, like voltage sags or power breakdowns. To cope with these disturbances, back-up energy storage devices are used, like uninterruptible power supplies (UPS) and flywheels. Some of these devices may use superconductivity. Commercial PE semiconductor devices (power diodes, power MOSFETs, IGBTs, power Darlington transistors and others) are rarely (or never) experimented for cryogenic temperatures, even when designed for military applications. This means that its integration with HTS power devices is usually done in the hot environment, raising several implementation restrictions. These reasons led to the natural desire of characterising PE under extreme conditions, e. g. at liquid nitrogen temperatures, for use in HTS devices. Some researchers expect that cryogenic temperatures may increase power electronics' performance when compared with room-temperature operation, namely reducing conduction losses and switching time. Also the overall system efficiency may increase due to improved properties of semiconductor materials at low temperatures, reduced losses, and removal of dissipation elements. In this work, steady state operation of commercial PE semiconductors and devices were investigated at liquid nitrogen and room temperatures. Performances in cryogenic and room temperatures are compared. Results help to decide which environment is to be used for different power HTS applications.

Pina, J., P. Pereira, S. Valtchev, A. Gonçalves, V. M. Neves, A. Alvarez, and L. Rodrigues, "A test rig for thrust force measurements of an all HTS linear synchronous motor", Journal of Physics: Conference Series, vol. 97, no. 1, pp. 012220, 2008. AbstractWebsite

This paper presents the design of a test rig for an all HTS linear synchronous motor. Although this motor showed to have several unattractive characteristics, its design raised a number of problems which must be considered in future HTS machines design. HTS electromagnetic properties led to the development of new paradigms in electrical machines and power systems, as e. g. in some cases iron removal and consequent assembly of lighter devices. This is due to superconductor's ability to carry high currents with minimum losses and consequent generation in the surrounding air of flux densities much higher than the allowed by ferromagnetic saturation. However, severe restrictions in HTS power devices design that goes further beyond cryogenic considerations must be accounted in. This is usually the case when BSCCO tapes are used as conductors. Its bending limitations and the presence of flux components perpendicular to tape surface, due to the absence of iron, have to be considered for it may turn some possible applications not so attractive or even practically unfeasible. An all HTS linear synchronous motor built by BSCCO tapes as armature conductors and two trapped-flux YBCO bulks in the mover was constructed and thrust force measurements are starting to be performed. Although the device presents severe restrictions due to the exposed and other reasons, it allowed systematising its design. A pulsed-field magnetiser to generate opposite fluxes for both YBCO bulks is also detailed. Thrust force numerical predictions were already derived and presented.