Gate-bias stress in amorphous oxide semiconductors thin-film transistors
- Citation:
- Lopes, M.E.a, Gomes Medeiros Barquinha Pereira Fortunato Martins Ferreira H. L. a M. "Gate-bias stress in amorphous oxide semiconductors thin-film transistors." Applied Physics Letters. 95 (2009).
Abstract:
A quantitative study of the dynamics of threshold-voltage shifts with time in gallium-indium zinc oxide amorphous thin-film transistors is presented using standard analysis based on the stretched exponential relaxation. For devices using thermal silicon oxide as gate dielectric, the relaxation time is 3× 105 s at room temperature with activation energy of 0.68 eV. These transistors approach the stability of the amorphous silicon transistors. The threshold voltage shift is faster after water vapor exposure suggesting that the origin of this instability is charge trapping at residual-water-related trap sites. © 2009 American Institute of Physics.
Notes:
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