Pessanha, Vasco, Ricardo J. Dias, João M. Lourenço, Eitan Farchi, and Diogo Sousa. "
Practical verification of high-level dataraces in transactional memory programs."
Proceedings of 9th the Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging. PADTAD'11. New York, NY, USA: ACM, 2011. 26-34.
AbstractIn this paper we present MoTh, a tool that uses static analysis to enable the automatic verification of concurrency anomalies in Transactional Memory Java programs. Currently MoTh detects high-level dataraces and stale-value errors, but it is extendable by plugging-in sensors, each sensor implementing an anomaly detecting algorithm. We validate and benchmark MoTh by applying it to a set of well known concurrent buggy programs and by close comparison of the results with other similar tools. The results achieved so far are very promising, yielding good accuracy while triggering only a very limited number of false warnings.
Martins, R., B. Brás, I. Ferreira, L. Pereira, P. Barquinha, N. Correia, R. Costa, T. Busani, A. Gonçalves, A. Pimentel, and E. Fortunato. "
{Away from silicon era: the paper electronics}." Eds. Ferechteh H. Teherani, David C. Look, and David J. Rogers. Vol. 7940. 2011. 79400P–10.
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Gabaldon, Alfredo, João Leite, and José Júlio Alferes. "
Evolving Logic Programs with Temporal Operators."
Logic Programming, Knowledge Representation, and Nonmonotonic Reasoning: Essays in Honor of Michael Gelfond. Eds. M. Balduccini, and T. Son. LNCS/LNAI. Springer, 2011. 193-212.
Abstract
Dias, Ricardo, João Louren{\c c}o, and Nuno Pregui{\c c}a. "
Efficient and Correct Transactional Memory Programs Combining Snapshot Isolation and Static Analysis."
Proceedings of the 3nd USENIX conference on Hot topics in parallelism (HotPar’11). HotPar’11. Usenix Association, 2011.
AbstractConcurrent programs may suffer from concurrency anomalies that may lead to erroneous and unpredictable program behaviors. To ensure program correctness, these anomalies must be diagnosed and corrected. This paper addresses the detection of both low- and high-level anomalies in the Transactional Memory setting. We propose a static analysis procedure and a framework to address Transactional Memory anomalies. We start by dealing with the classic case of low-level dataraces, identifying concurrent accesses to shared memory cells that are not protected within the scope of a memory transaction. Then, we address the case of high-level dataraces, bringing the programmer’s attention to pairs of memory transactions that were misspecified and should have been combined into a single transaction. Our framework was applied to a set of programs, collected form different sources, containing well known low- and high-level anomalies. The framework demonstrated to be accurate, confirming the effectiveness of using static analysis techniques to precisely identify concurrency anomalies in Transactional Memory programs.
Oliveira, Luís Picciochi, and João M. Lourenço. "
Aceleração de Computações Científicas com Processadores Heterogéneos."
InForum 2011: Proceedings of InForum Simpósio de Informática. Coimbra: Universidade do Coimbra, 2011.
AbstractActualmente o mercado residencial de computadores inclui não só multiprocessadores com diversos núcleos (CPUs) como também placas gráficas (GPUs) cuja capacidade de processamento tem evoluído a um ritmo exponencial. Este poder computacional pode ser utilizado para outros fins para além do processamento gráfico, tal como o processamento de algoritmos comuns em computação científica. Neste artigo é apresentada, discutida e avaliada a framework Cheetah, uma framework que distribui programas computacionalmente exigentes sobre uma rede de CPUs e GPUs. Um programador que utilize a Cheetah apenas necessita de especificar o seu programa como um conjunto de kernels OpenCL, relegando para a framework a distribuição destes pelas unidades de processamento disponíveis. O programa pode assim escalar à medida que são adicionados novos recursos computacionais, sem quaisquer esforços adicionais de adaptação ou recompilação. Os testes realizados demonstraram a capacidade de a framework providenciar aceleracçõs até duas ordens de grandeza com um esforço de desenvolvimento reduzido, mesmo quando na presença de recursos computacionais limitados.
Lewandowski, B., A. Listkowski, K. T. Petrova, and S. Jarosz. "
Functionalisation of terminal positions of sucrose - Part II: Preparation of 1’,2,3,3’,4,4’-hexa-O-benzyl sucrose and 6,6’-bis-O-(2-hydroxyethyl)-1’,2,3,3’,4,4’-hexa-O-benzylsucrose."
Carbohydrate Chemistry: Proven Synthetic Methods. Ed. P. Kovac. Taylor & Francis Group: CRC Press, 2011. 407-425.
Amado, M. P., T. Lopes, and J. C. Freitas Green Building Process. World Congress of Sustainable Building. Helsinki, Finland: SB11, 2011.