Novel linear analog-adder using a-IGZO TFTs
- Citation:
- Bahubalindruni, P.G.a c, Tavares Fortunato Martins Barquinha V. G. b E. "Novel linear analog-adder using a-IGZO TFTs." Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 2016-July. 2016. 2098-2101.
Abstract:
A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200° C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of ≈ 4 pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 μW and a bandwidth of ≈ 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics. © 2016 IEEE.
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