n/a

n/a

Transactional Memory allows programmers to reduce the number of synchronization errors introduced in concurrent programs, but does not ensures its complete elimination. This paper proposes a pattern matching based approach to the static detection of atomicity violation, based on a path-sensitive symbolic execution method to model four anomalies that may affect Transactional Memory programs. The proposed technique may be used to to bring to programmer's attention pairs of transactions that the programmer has mis-specified, and should have been combined into a single transaction. The algorithm first traverses the AST tree, removing all the non-transactional blocks and generating a trace tree in the path sensitive manner for each thread. The trace tree is a Trie like data structure, where each path from root to a leaf is a list of transactions. For each pair of threads, erroneous patterns involving two consecutive transactions are then checked in the trace tree. Results allow to conclude that the proposed technique, although triggering a moderate number of false positives, can be successfully applied to Java programs, correctly identifying the vast majority of the relevant erroneous patterns.

The traditional methodology used in civil engineering measurements requires a lot of equipment and a very complex procedure especially if the number of target points increase. Since the beginning of the current century, several studies have been conducted in the area of photogrametry using digital image
correlation associated with block motion algorithms to estimate displacements in reinforced concrete (RC) beams during a load test. Using image processing techniques it is possible to measure the whole area of interest and not only a few points of the tests materials. In this paper, block-matching algorithms are used in order to compare the results from photogrametry techniques and the data obtained with linear voltage displacement transducer (LVDT) sensors during the load tests of RC beams, which are very common to find in civil engineering laboratories.

Domain Specic Languages (DSLs) can contribute to increment productivity, while reducing the required maintenance and programming expertise. We hypothesize that Software Languages Engineering (SLE) developers consistently skip, or relax, Language Evaluation. Based on the experience of engineering other types of software products, we assume that this may potentially lead to the deployment of inadequate languages. The fact that the languages already deal with concepts from the problem domain, and not the solution domain, is not enough to validate several issues at stake, such as its expressiveness, usability,
effectiveness, maintainability, or even the domain expert's productivity while using them. We present a systematic review on articles published in top ranked venues, from 2001 to 2008, which report DSLs' construction, to characterize the common practice. This work conrms our initial hypothesis and lays the ground for the discussion on how to include a systematic approach to DSL evaluation in the SLE process.

Spreadsheets are widely used by end users, and studies have shown that most end-user spreadsheets contain non-trivial errors. To improve end users productivity, recent research proposes the use of a model-driven engineering approach to spreadsheets. In this paper we conduct the first systematic empirical study to assess the effectiveness and efficiency of this approach. A set of spreadsheet end users worked with two different model-based spreadsheets, and we present and analyze the results achieved.

n/a

This work introduces a tool for the optimization of CMOS integrated spiral inductors. The main objective of this tool is to offer designers a first approach for the determination of the inductor layout parameters. The core of the tool is a Genetic Algorithm (GA) optimization procedure where technology constraints on the inductor layout parameters are considered. Further constraints regarding inductor design heuristics are also accounted for. Since the layout parameters are inherently discrete due to technology and topology constraints, discrete variable optimization techniques are used. The Matlab GA toolbox is used and the modifications on the GA functions, yielding technology feasible solutions is presented. For the sake of efficiency and simplicity the pi-model is used for characterizing the inductor. The validity of the design results obtained with the tool, is checked against circuit simulation with ASITIC.