{Bias Stress and Temperature Impact on InGaZnO TFTs and Circuits}
- Citation:
- Martins, Jorge, Pydi Bahubalindruni, Ana Rovisco, Asal Kiazadeh, Rodrigo Martins, Elvira Fortunato, and Pedro Barquinha. "{Bias Stress and Temperature Impact on InGaZnO TFTs and Circuits}." Materials. 10 (2017): 680.
Abstract:
This paper focuses on the analysis of InGaZnO thin-film transistors (TFTs) and circuits under the influence of different temperatures and bias stress, shedding light into their robustness when used in real-world applications. For temperature-dependent measurements, a temperature range of 15 to 85 • C was considered. In case of bias stress, both gate and drain bias were applied for 60 min. Though isolated transistors show a variation of drain current as high as 56% and 172% during bias voltage and temperature stress, the employed circuits were able to counteract it. Inverters and two-TFT current mirrors following simple circuit topologies showed a gain variation below 8%, while the improved robustness of a cascode current mirror design is proven by showing a gain variation less than 5%. The demonstration that the proper selection of TFT materials and circuit topologies results in robust operation of oxide electronics under different stress conditions and over a reasonable range of temperatures proves that the technology is suitable for applications such as smart food packaging and wearables.
Notes:
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