André Lopes (2010)

MSc Student

in

MSc dissertation: tlCell: a Software Transactional Memory for the Cell Broadband Engine Architecture   
Period: September 2008 — June 2010
Grade: 15/20

The evolution of computers grew exponentially in the last decades. The performance has always been the main concern resulting in increasing clock frequency of processors, which is not feasible anymore due to power consumption of actual energy-starving processors. Cell Broadband Engine Architecture project started with the goal of deliver high performance with low power consumption. The result is a heterogeneous multiprocessor architecture with a unique memory design space towards high performance and reduced hardware complexity to reduce the cost of production. In such an architecture it is expected that concurrency and parallelism techniques improve performance substantially, however the high performance solutions presented for CBEA are very specific due to its novel architecture and memory distribution and it is still hard to develop tools that are able to provide to the programmer an abstraction layer that is able to exploit concurrency and manage consistency. Software Transactional Memory is a programming model that proposes this abstraction layer, and is gaining increased popularity and several prototypes have been developed with performance close to fine-grain specific implementations for the domain problem. The possibility of using STM to develop a tool capable of hiding all the memory management and consistency in CBEA is very appellative. In this document we specify a deferred-update STM framework for CBEA that takes advantage of the SPEs for computational power using a commit-time locking mechanism for committing transactions. Also two different models are proposed, fully local and multi-buffered models in order to better study the implications of our design choices.

Keywords: Software Transactional Memory, Cell Broadband Engine Architecture, Consistent Transaction Layer.