The purpose of this paper is to establish links between supply chain disturbances and corresponding strategies of resilience to counter them. To this end, an inductive research approach is used, examining a sample of 38 cases. Secondary data from the cases is used to identify disturbances which affected the corresponding supply chains and the resilience strategies used by managers. The empirical evidences shows that the negative effects of supply chain disturbances can be categorised into a number of supply chain failure modes. In addition, a set of resilience strategies was identified that could be used to overcome those failure modes. A conceptual model, with links between supply chain disturbances, failures and resilience strategies, is proposed. The limitations of this research result from the use of secondary data sources. The findings are only valid for the selected case studies and, consequently, may not be applicable in other scenarios. Future research should focus on detailed case studies that investigate cross-functional applications across the organisation and the supply chain.

The potential advantage of using superconducting materials in electrical devices is well described in the literature. The electromagnetic properties of these materials make them unique for several applications, such as, e.g. electrical machines and drives, fault current applications, or superconducting magnetic energy storage. In the development of electromechanical conversion devices, superconducting materials are used foreseeing mainly a decrease in the device dimensions or a performance improvement for the same active volume. To guarantee a good application of this kind of materials it is important to describe and model the phenomena that characterize their operation under different regimes. In this paper, a study based in FEM simulations of a motor with bulk superconductor in the rotor is carried out, with the purpose of understand, quantify and qualify which phenomena are present in the different regimes of the motor, leading to obtaining an equivalent electrical circuit with lumped parameters.

The microstructural aspects related to crystalline or amorphous structure of as-deposited and annealed films of sol-gel-derived WO 3 are shown in the literature to be critical for electrochromic (EC) performance. In consideration of ion insertion materials, there is a need for developing light and at the same time nanocrystalline structures to improve both coloration efficiency and switching kinetics. By controlling microstructure and morphology, one could design a material with optimal EC performance. This report compares the microstructural and morphological characteristics of standard WO 3 wet deposition techniques versus inkjet printing technology (IPT), correlating these features with their optical and electrochemical performances, emphasizing the importance of the dual-phase a-WO 3/TiO 2/WO X film composition proposed in this work for high-performance EC applications. The effect of the type and content of metal oxide nanoparticles in the precursor sols formulated in various peroxopolytungstic acid (PTA) and oxalic acid (OAD) proportions on film properties is comprehensively studied using multi-factorial design of experiment (DOE). To the authors' knowledge, no other report on sol-gel deposition of inorganic EC materials via the inkjet printing technique exists, in which furthermore the film crystallinity can be controlled under low-temperature process conditions. The proposed method enables development of EC films which irrespective of their composition (a-WO 3, a-WO 3/TiO 2 or a-WO 3/TiO 2/WO X) outperform their amorphous or nanocrystalline analogues presented as the state-of-the-art due to their superior chemical and physical properties. © 2012 The Royal Society of Chemistry.

Inductive superconducting fault current limiters have already demonstrated their technical viability in electrical networks. Its architecture and robustness make them potentially adequate for distribution networks, and this type of devices is considered as an enabling technology for the advent of embedded generation with renewable energy sources. In order to promote the growth and maturity of these superconducting technologies, fast design tools must be developed, allowing simulating devices with different materials in grids with diverse characteristics. This work presents advances in the development of such tool, which, at present stage, is an effective alternative to software simulations by finite elements methods, reducing dramatically computation time. The algorithms are now compared with experimental results from a laboratory scale prototype, showing the need to refine them.

Reduction in the accumulation capacitance value was more in Si metal-oxide-semiconductor devices than that of Ge metal-oxide-semiconductor devices after a thermal treatment irrespective of the annealing environment. Relatively, thermal treatment in oxygen environment improves the interface quality of HfO2/Ge stacks considerably, when compared with HfO 2/Si stacks. Whereas, the forming gas annealing at a temperature of 400 °C was not so effective in improving the interface quality at HfO 2/Si stack. The presence of induced negatively charged hydrogen atom in Ge lessens the Fermi level pinning at HfO2 and Ge interface. © 2011 Elsevier B.V. All rights reserved.

In this work we present sputtered multicomponent dielectrics based on mixtures of HfO 2 and SiO 2. This way it is possible to get stable amorphous structure up to 800°C, that does not happen for pure HfO 2, for instance, that present a polycrystalline structure when deposited without any intentional substrate heating. Besides, also the band gap of the resulting films is increased when compared with pure HfO2 that theoretically is an advantage in getting a suitable band offset with the semiconductor layer on oxide TFTs. Concerning the electrical characterization, the leakage current on c-Si MIS structures is low as 10 -9 Acm -2 at 10 V. The amorphous structure of the films also lead to better dielectric/semiconductor interfaces, as suggested by C-V characteristics on GIZO MIS structures, which do not present strong variation with frequency. On other hand, the dielectric constant decreases due to the incorporation of SiO 2 and Al 2O 3. Further improvement on insulating and interface characteristics is achieved using multilayer stacks and substrate bias during deposition. © 2012 Copyright Society of Photo-Optical Instrumentation Engineers (SPIE).

This paper presents the results of a preliminary study to examine the ability of post-silicon devices for analog processing. It is focused on the latest thin-film transistors (TFTs) with amorphous gallium-indium-zinc oxide (a-GIZO) as active layer. Three circuit configurations are presented: a differential pair and two multiplier topologies. Both triode and saturation regions of operation are included in the analysis, with the devices set to remain in strong accumulation. A neural model, which is developed based on the measured data of the TFTs, is used for the circuit simulations in the Cadence Virtuoso environment. The analog multipliers simulation results are compared against the expected functional results. © 2012 IEEE.

This chapter gives an overview about GIZO TFTs, comprising an introductory section about generic TFT structure and operation, different semiconductor technologies for TFTs - with special emphasis on AOSs and particularly on GIZO - and then some experimental results obtained for GIZO TFTs fabricated in CENIMAT. Thin-film transistors (TFTs) are important electronic devices which are predominantly used as On/Off switches in active matrix backplanes of flat panel displays (FPDs), namely liquid crystal displays (LCDs) and organic light emitting device (OLED) displays. Even if a-Si:H is still dominating the TFT market in terms of semiconductor technology, oxide semiconductors are emerging as one of the most promising alternatives for the next generation of TFTs, bringing the possibility of having fully transparent devices, low processing temperature, low cost, high performance and electrically stable properties [1, 2]. Amorphous oxide semiconductors (AOS) such as Gallium-Indium-Zinc oxide (GIZO) [3, 4], even if fabricated at temperatures below 150°, are currently capable of providing transistors with field-effect mobility (μFE) exceeding 20 cm2V-1 s-1, threshold voltage (VT) close to 0V, On/Off ratios above 108, subthreshold swing (S) around 0:20V dec-1 and fully recoverable VT shift (ΔVT) lower than 0.5V after 24 h stress with constant drain current of 10 μA. © Springer-Verlag Berlin Heidelberg 2012.