Ana Rovisco

Poly(p-xylylene) derivatives, widely known as Parylenes, have been considerably adopted by the scientific community for several applications, ranging from simple passive coatings to active device components. Here, we explore the thermal, structural, and electrical properties of Parylene C, and further present a variety of electronic devices featuring this polymer: transistors, capacitors, and digital microfluidic (DMF) devices. We evaluate transistors produced with Parylene C as a dielectric, substrate, and encapsulation layer, either semitransparent or fully transparent. Such transistors exhibit steep transfer curves and subthreshold slopes of 0.26 V/dec, negligible gate leak currents, and fair mobilities. Furthermore, we characterize MIM (metal–insulator–metal) structures with Parylene C as a dielectric and demonstrate the functionality of the polymer deposited in single and double layers under temperature and AC signal stimuli, mimicking the DMF stimuli. Applying temperature generally leads to a decrease in the capacitance of the dielectric layer, whereas applying an AC signal leads to an increase in said capacitance for double-layered Parylene C only. By applying the two stimuli, the capacitance seems to suffer from a balanced influence of both the separated stimuli. Lastly, we demonstrate that DMF devices with double-layered Parylene C allow for faster droplet motion and enable long nucleic acid amplification reactions.

The degradation of organic pollutants in wastewaters assisted by oxide semiconductor nanostructures has been the focus of many research groups over the last decades, along with the synthesis of these nanomaterials by simple, eco-friendly, fast, and cost-effective processes. In this work, porous zinc oxide (ZnO) nanostructures were successfully synthesized via a microwave hydrothermal process. A layered zinc hydroxide carbonate (LZHC) precursor was obtained after 15 min of synthesis and submitted to different calcination temperatures to convert it into porous ZnO nanostructures. The influence of the calcination temperature (300, 500, and 700 °C) on the morphological, structural, and optical properties of the ZnO nanostructureswas investigated. All ZnO samples were tested as photocatalysts in the degradation of rhodamine B (RhB) under UV irradiation and natural sunlight. All samples showed enhanced photocatalytic activity under both light sources, with RhB being practically degraded within 60 min in both situations. The porous ZnO obtained at 700 °C showed the greatest photocatalytic activity due to its high crystallinity, with a degradation rate of 0.091 and 0.084 min−1 for UV light and sunlight, respectively. These results are a very important step towards the use of oxide semiconductors in the degradation of water pollutants mediated by natural sunlight.

In this article, characterization of fully patterned zinc-tin oxide (ZTO)-based memristive devices with feature sizes as small as 25 µm2 is presented. The devices are patterned via lift-off with a platinum bottom contact and a gold-titanium top contact. An on/off ratio of more than two orders of magnitude is obtained without the need for electroforming processes. Set operation is a current controlled process, whereas the reset is voltage dependent. The temperature dependency of the electrical characteristics reveals a bulk-dominated conduction mechanism for high resistance states. However, the charge transport at low resistance state is consistent with Schottky emission. Synaptic properties such as potentiation and depression cycles, with progressive increases and decreases in the conductance value under 50 successive pulses, are shown. This validates the potential use of ZTO memristive devices for a sustainable and energy-efficient brain-inspired deep neural network computation.

Co-sputtering of SiO2 and high-$ąppa$ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-$ąppa$ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-$ąppa$ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO2 both mixed with Ta2O5 and as thin interfacial layers. A stack comprising a (Ta2O5)x(SiO2)100 − x film with x = 69 and a thin SiO2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (µFE) ≈ 16 cm2·V−1·s−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 107. Anomalous Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 105 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.

This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register) and row-selector (a frequency divider and a shift register). They are realised with rail-to-rail logic gates with level-shifting ability that can perform inversion and NAND logic operations. These logic gates are capable of providing full output swing between supply rails, $V_{DD}$ and $V_{SS}$ , by introducing a single additional switch for each input in bootstrapping logic gates. These circuits were characterised under normal ambient atmosphere and show an improved performance compared to the conventional logic gates with diode connected load and pseudo CMOS counterparts. By using these high-performance logic gates, a complete rail-to-rail frequency divider is presented from measurements using D-Flip Flop. In order to realize a complete compact system, an on-chip ring oscillator (output clock frequency around 1 kHz) and a shift register are also presented from simulations, where these circuits show a power consumption of 1.5 mW and 0.82 mW at a supply voltage of 8 V, respectively. While the circuit concepts described here were designed for an X-ray sensing system, they can be readily expanded to other domains where flexible on-chip timing signal generation is required, such as, smart packaging, biomedical wearable devices and RFIDs.

Ca1-xSmxMnO3 (0≤x≤0.4) films were successfully fabricated on Indium Tin Oxide (ITO) coated quartz glass substrates by radio frequency magnetron sputtering technique (RF- magnetron sputtering) from compacted nanosized powder targets, and subsequent annealing at 800°C in air, for 6h. X-ray diffraction shows a pure typical perovskite phase for x≥0.1. Scanning electron microscopy and atomic force microscopy revealed that the film surface is dense, with low roughness, depending on the Sm content, even though a few cracks were observed. Crystallite size was found to decrease with the Sm content. The electrodes were characterized by cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS).The oxide electrode's capacitance was estimated using both techniques and the corresponding roughness factors evaluated. The values obtained from the two methods show a good agreement. A comparison between the voltammetric data and those referred in the literature allowed finding out that the redox reaction occurring at the electrode surface involves the pair Mn4+/Mn3+. EIS measurements confirm the voltammetric data and they also give additional information about the film porosity and the charge transfer resistance. This last parameter is associated with the oxidation and reduction of the pair Mn3+/Mn4+and after normalized by the roughness factor shows an increase with samarium content.