Ana Rovisco

In this article, characterization of fully patterned zinc-tin oxide (ZTO)-based memristive devices with feature sizes as small as 25 µm2 is presented. The devices are patterned via lift-off with a platinum bottom contact and a gold-titanium top contact. An on/off ratio of more than two orders of magnitude is obtained without the need for electroforming processes. Set operation is a current controlled process, whereas the reset is voltage dependent. The temperature dependency of the electrical characteristics reveals a bulk-dominated conduction mechanism for high resistance states. However, the charge transport at low resistance state is consistent with Schottky emission. Synaptic properties such as potentiation and depression cycles, with progressive increases and decreases in the conductance value under 50 successive pulses, are shown. This validates the potential use of ZTO memristive devices for a sustainable and energy-efficient brain-inspired deep neural network computation.

Co-sputtering of SiO2 and high-$ąppa$ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-$ąppa$ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-$ąppa$ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO2 both mixed with Ta2O5 and as thin interfacial layers. A stack comprising a (Ta2O5)x(SiO2)100 − x film with x = 69 and a thin SiO2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (µFE) ≈ 16 cm2·V−1·s−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 107. Anomalous Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 105 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.