<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Mikhail Mudrov</style></author><author><style face="normal" font="default" size="100%">Anatoliy Zyuzev</style></author><author><style face="normal" font="default" size="100%">Konstantin Nesterov</style></author><author><style face="normal" font="default" size="100%">Stanimir Valtchev</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model</style></title><secondary-title><style face="normal" font="default" size="100%">Conference Proceedings - 2017 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017</style></secondary-title></titles><keywords><keyword><style  face="normal" font="default" size="100%">FPGA</style></keyword><keyword><style  face="normal" font="default" size="100%">HiL</style></keyword><keyword><style  face="normal" font="default" size="100%">HiL accuracy</style></keyword><keyword><style  face="normal" font="default" size="100%">induction motor</style></keyword><keyword><style  face="normal" font="default" size="100%">Real-time simulating</style></keyword></keywords><dates><year><style  face="normal" font="default" size="100%">2017</style></year><pub-dates><date><style  face="normal" font="default" size="100%">7</style></date></pub-dates></dates><publisher><style face="normal" font="default" size="100%">Institute of Electrical and Electronics Engineers Inc.</style></publisher><pub-location><style face="normal" font="default" size="100%">United States</style></pub-location><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">&lt;p&gt;The Hardware-in-the-Loop (HiL) systems become nowadays popular. In the same time, the Field Programmable Gate Arrays (FPGAs) allow for creating the HiL with time step 1 μs or less. The FPGA usually executes the numerical operations on Fixed Point variables. That is why during the FPGA-based HiL creation process it is important to select a proper number of bits for the modeled variables. A mathematical model based on the induction motor is selected as a basis for comparative tests between the floating point model and the fixed point model. In consequence, recommendations for the Bit Capacity (the length of the digital word) selection are given, based on the obtained results.&lt;/p&gt;
</style></abstract><notes><style face="normal" font="default" size="100%">&lt;p&gt;sem pdf conforme despacho.&lt;/p&gt;
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