<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Martins, R., Fantoni, A., Vieira, M.</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Tailoring defects on amorphous silicon pin devices</style></title><secondary-title><style face="normal" font="default" size="100%">Journal of Non-Crystalline Solids</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">1993</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">https://www.scopus.com/inward/record.uri?eid=2-s2.0-0027906850&amp;partnerID=40&amp;md5=820421f6a25492df214107ec99a3bab0</style></url></web-urls></urls><number><style face="normal" font="default" size="100%">PART 2</style></number><volume><style face="normal" font="default" size="100%">164-166</style></volume><pages><style face="normal" font="default" size="100%">671-674</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">&lt;p&gt;This paper deals with a new model and structure able to tailor defects in pin devices. The model assumes the usual density of states profile, including donor and acceptor like states inside the mobility gap and has the capability to simulate the transient and steady state device behavior. The new structure is based in two interfacial defectous layers, located at the junctions, acting as &quot;gettering&quot; centers to tailor the defects. The role of the interlayer and its thickness on device performances will be also discussed. © 1993.&lt;/p&gt;
</style></abstract><notes><style face="normal" font="default" size="100%">&lt;p&gt;cited By 13&lt;/p&gt;
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