<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="6.x">Drupal-Biblio</source-app><ref-type>47</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">P Pereira</style></author><author><style face="normal" font="default" size="100%">Fino, H.</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">VCOSYM -an application for the automatic design of ring VCOS</style></title><secondary-title><style face="normal" font="default" size="100%">Proc. 12th IEEE Int. Conf. Electronics, Circuits and Systems ICECS 2005</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2005</style></year></dates><urls><web-urls><url><style face="normal" font="default" size="100%">http://dx.doi.org/10.1109/ICECS.2005.4633504</style></url></web-urls></urls><pages><style face="normal" font="default" size="100%">1–4</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">&lt;p&gt;This paper presents an application for the automatic design of ring VCOs. In this application a VCO model based on the Npower transistor model is considered as a away of granting the accuracy of results for submicron technologies. In order to easily integrate any VCO previously designed into a PLL automatic design tool, a corresponding linear model of the VCO is automatically generated, yielding a simple and precise characterization for higher level system design. The design of a 150 MHz VCO using a seven stage ring topology is presented. The validity of the design obtained is checked against Hspice simulation of the circuit.&lt;/p&gt;
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