Kchaou, O. B., A. Sallem, P. Pereira, M. Fakhfakh, and M. H. Fino,
"Multi-objective sensitivity-based optimization of analog circuits exploiting NSGA-II front ranking",
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015 International Conference on, Istanbul, Turkey, pp. 1-4, Sept, 2015.
AbstractThis work deals with the multi-objective optimization of analog circuits by generating the Pareto front where elements are low sensitive to parameters' variations. NSGA-II is used for obtaining the non-dominated solutions. Richardson extrapolation technique is used for the in-loop optimization approach for computing partial derivatives and, thus, the solutions' sensitivity. NSGA-II Pareto fronts' intrinsic ranking is exploited for the generation of the new ‘low-sensitive’ Pareto front. The case of the optimal sizing of a CMOS voltage follower is considered to exemplify the proposed approach.
Kchaou, B. O., A. Garbaya, M. Kotti, P. Pereira, M. Fakhfakh, and H. M. Fino,
"Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits",
Integration, the \{VLSI\} Journal, vol. 55, pp. 220 - 226, 2016.
AbstractAbstract This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters' variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation \{CMOS\} current conveyor and a \{CMOS\} voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.
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