@conference {inforum:2015:rmonteiro, title = {Como separar o trigo do joio? Ou: Como selecionar a melhor fotografia de um conjunto de fotografias semelhantes}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, series = {INForum 2015}, year = {2015}, note = {

n/a

}, month = {sep}, address = {Covilh{\~a}, Portugal}, abstract = {

O advento da fotografia digital est{\'a} na base de uma clara mudan{\c c}a de paradigma no processo de gest{\~a}o da fotografia por amadores. Porque tirar mais uma fotografia agora n{\~a}o representa qualquer custo adicional, {\'e} frequente tirarem-se m{\'u}ltiplas fotografias ao mesmo sujeito, na expectativa de que uma delas corresponda aos padr{\~o}es de qualidade desejados, em termos de ilumina{\c c}{\~a}o, foco e enquadramento. Assumindo que a quest{\~a}o do enquadramento se resolve facilmente recorrendo ao recorte (crop) da fotografia, tem-se ainda assim que selecionar qual das v{\'a}rias fotografias bem enquadradas, tecnicamente parecidas em termos de ilumina{\c c}{\~a}o e foco, vamos guardar (e por oposi{\c c}{\~a}o quais vamos descartar). A escolha da melhor fotografia com base na observa{\c c}{\~a}o visual em ecr{\~a} de computador {\'e} um processo muito pouco preciso e, portanto, gerador de sensa{\c c}{\~o}es de inseguran{\c c}a que resultam, muitas vezes, na op{\c c}{\~a}o de n{\~a}o descartar nenhuma das v{\'a}rias fotografias semelhantes. Neste artigo propomo-nos endere{\c c}ar a quest{\~a}o de como ajudar um fot{\'o}grafo amador a selecionar a melhor fotografia de um conjunto de fotografias semelhantes em termos t{\'e}cnicos (foco e ilumina{\c c}{\~a}o) e de enquadramento. Este processo {\'e} baseado num workflow suportado por um pacote de software, que com alguma ajuda do utilizador permite ordenar um conjunto de fotografias semelhantes, sendo assim poss{\'\i}vel escolher aquela que melhor corresponde {\`a}s expectativas e dando seguran{\c c}a e conforto na eventual elimina{\c c}{\~a}o das restantes.

}, keywords = {Fotografia digital, Processamento de imagem, Sistema de apoio {\`a} decis{\~a}o}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum15-photo.pdf}, author = {Andr{\'e} Alves and Fernando P. Birra and Jo{\~a}o M. Louren{\c c}o} } @conference {inforum:2015:rmonteiro, title = {Um Armazenamento Distribu{\'\i}do para uma Rede de Dispositivos M{\'o}veis}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, series = {INForum 2015}, year = {2015}, note = {

n/a

}, month = {sep}, address = {Covilh{\~a}, Portugal}, abstract = {

Os dispositivos m{\'o}veis em proximidade geogr{\'a}fica representam um conjunto de recursos inexplorados, tanto em termos de capacidade de processamento como de rmazenamento, o que abre caminho para novas aplica{\c c}{\~o}es com oportunidades e desafios {\'u}nicos. Os sistemas atuais de partilha de dados (e. g., fotos, m{\'u}sica, v{\'\i}deos) para dispositivos m{\'o}veis exigem que exista conectividade com a Internet para funcionarem. No entanto, em ambientes onde a conectividade com a Internet n{\~a}o {\'e} constante ou de boa qualidade (e. g., eventos desportivos e concertos), ou em locais remotos onde as infraestruturas de rede n{\~a}o existem, {\'e} dif{\'\i}cil (ou mesmo imposs{\'\i}vel) partilhar dados entre v{\'a}rios dispositivos m{\'o}veis. Para resolver este problema, os dispositivos m{\'o}veis podem formar uma rede ad hoc para compartilhar os seus dados e recursos. Neste artigo propomos um sistema de armazenamento distribu{\'\i}do para partilha de dados entre dispositivos m{\'o}veis de uso di{\'a}rio, e. g., smartphones e tablets, usando um mecanismo de melhor esfor{\c c}o para garantir persist{\^e}ncia e disponibilidade de dados suportando churn (entrada e sa{\'\i}da inesperada de dispositivos).

}, keywords = {Dispositivos M{\'o}veis, Peer-to-Peer, Redes ad hoc}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum2015-rmonteiro.pdf}, author = {Ricardo Monteiro and Jo{\~a}o M. Louren{\c c}o and Paulino, Herv{\'e}} } @article {strv:2015:efarchi, title = {Special issue on Testing, Analysis and Debugging of Concurrent Programs}, journal = {Software Testing, Verification and Reliability}, volume = {25}, number = {3}, year = {2015}, note = {n/a}, month = {May}, pages = {165{\textendash}166}, abstract = {

This special issue concerns a range of issues related to the development of concurrent programs. This is an important topic, because many systems are now either multi-threaded or distributed, and it is well known that concurrency makes testing, analysis and debugging significantly more complicated. Essentially, the alternative interleavings of events can lead to different behaviours, and so any analysis, debugging or testing technique must consider these interleavings. The interest in this topic is reflected in the larger than normal issue, which contains five papers. The papers fall into three groups: we start with a paper on debugging, then have two on static analysis techniques and finally have two on testing. All papers were reviewed in the normal way.

}, issn = {1099-1689}, doi = {10.1002/stvr.1577}, url = {http://doi.org/10.1002/stvr.1577}, author = {Farchi, Eitan and Hierons, Robert M. and Jo{\~a}o M. Louren{\c c}o} } @conference {icdcnsrf:2015:jsilva, title = {Crowd-Sourcing Mobile Devices to Provide Storage in Edge-Clouds}, booktitle = {Proceedings of the Doctoral Symposium of the 16th International Conference on Distributed Computing and Networking}, series = {ICDCN 2015}, year = {2015}, note = {

n/a

}, month = {Jan}, abstract = {

Given the proliferation and enhanced capabilities of mobile devices, their computational and storage resources can now be combined in a wireless cloud of nearby mobile devices, a mobile edge-cloud. These clouds are of particular interest in low connectivity scenarios, e.g., sporting events and disaster scenarios. In these dynamic clouds it is necessary to reliably disseminate and share data, and also to offload data processing computations to other devices in the edge-cloud. We are particularly interested in supporting storage services in these new type of edge-clouds, as a mean to enable data sharing, dissemination and querying, as well as to serve as a distributed file system for offloaded computations. In this Ph.D. thesis, we propose to address these questions by researching on the usage of ad-hoc clouds of mobile devices to develop an efficient storage service capable of providing high availability and reliability.

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/icdcn15srf.pdf}, author = {Silva, Jo{\~a}o A. and Paulino, Herv{\'e} and Jo{\~a}o M. Louren{\c c}o} } @conference {sac:2015:jsilva, title = {Boosting Locality in Multi-version Partial Data Replication}, booktitle = {Proceedings of the 30th ACM/SIGAPP Symposium On Applied Computing (SAC{\textquoteright}15)}, year = {2015}, note = {

n/a

}, abstract = {

n/a

}, doi = {10.1145/2695664.2695851}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/sac15_cache.pdf}, author = {Jo{\~a}o Silva and Jo{\~a}o M. Louren{\c c}o and Paulino, Herv{\'e}} } @conference {eurocast:2015:jfiedor, title = {Dynamic Validation of Contracts in Concurrent Code}, booktitle = {Proceedings of the Fifteenth International Conference on Computer Aided Systems Theory (EUROCAST{\textquoteright}15)}, year = {2015}, note = {

(Extended Abstract)

}, publisher = {Universidad de Las Palmas de Gran Canaria}, organization = {Universidad de Las Palmas de Gran Canaria}, address = {Las Palmas de Gran Canaria, Spain}, abstract = {

Multi-threaded programs allow one to achieve better performance by doing a lot of work in parallel using multiple threads. Such parallel programs often contain code blocks that a thread must execute atomically, i.e., with no interference from the other threads of the program. Failing to execute these code blocks atomically leads to errors known as atomicity violations. However, frequently it not obvious to tell when a piece of code should be executed atomically, especially when that piece of code contains calls to some third-party library functions, about which the programmer has little or no knowledge at all. One solution to this problem is to associate a contract with such a library, telling the programmer how the library functions should be used, and then check whether the contract is indeed respected. For contract validation, static approaches have been proposed, with known limitations on precision and scalability. In this paper, we propose a dynamic method for contract validation, which is more precise and scalable than static approaches.

}, url = {https://dl.dropboxusercontent.com/u/4169746/Extended_Abstract_Book.pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/eurocast15.pdf}, author = {Jan Fiedor and Zdenek Letko and Jo{\~a}o M. Louren{\c c}o and Tomas Vojnar}, editor = {Alexis Quesada-Arencibia and Jos{\'e} Carlos Rodr{\'\i}guez and Roberto Moreno-D{\'\i}az jr. and Roberto Moreno-D{\'\i}az} } @conference {inforum:2015:tvale, title = {Execu{\c c}{\~a}o concorrente e determinista de transa{\c c}{\~o}es}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, series = {INForum 2015}, year = {2015}, note = {

n/a

}, address = {Covilh{\~a}, Portugal}, abstract = {

Neste artigo apresentamos um protocolo de controlo de concorr{\^e}ncia que garante que a execu{\c c}{\~a}o concorrente de transa{\c c}{\~o}es {\'e} equivalente {\`a} sua execu{\c c}{\~a}o sequencial por uma ordem predefinida. Isto permite executar programas que usam transa{\c c}{\~o}es de forma determinista. O protocolo (1) permite, pela primeira vez, a execu{\c c}{\~a}o determinista de programas que usam mem{\'o}ria transacional por hardware; e (2) garante a execu{\c c}{\~a}o determinista de programas que usam mem{\'o}ria transacional por software com um desempenho claramente superior ao estado da arte.

}, keywords = {Fotografia digital, Processamento de imagem, Sistema de apoio {\`a} decis{\~a}o}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum15-pot.pdf}, author = {Tiago Vale and Ricardo J. Dias and Silva, Jo{\~a}o A. and Jo{\~a}o M. Louren{\c c}o} } @inbook {eurotmbook:2015:rdias, title = {Framework Support for the Efficient Implementation of Multi-version Algorithms}, booktitle = {Transactional Memory. Foundations, Algorithms, Tools, and Applications}, series = {Lecture Notes in Computer Science}, volume = {8913}, year = {2015}, note = {

n/a

}, pages = {166{\textendash}191}, publisher = {Springer International Publishing}, organization = {Springer International Publishing}, abstract = {

Software Transactional Memory algorithms associate metadata with the memory locations accessed during a transactions lifetime. This metadata may be stored in an external table and accessed by way of a function that maps the address of each memory location with the table entry that keeps its metadata (this is the out-place or external scheme); or alternatively may be stored adjacent to the associated memory cell by wrapping them together (the in-place scheme). In transactional memory multi-version algorithms, several versions of the same memory location may exist. The efficient implementation of these algorithms requires a one-to-one correspondence between each memory location and its list of past versions, which is stored as metadata. In this chapter we address the matter of the efficient implementation of multi-version algorithms in Java by proposing and evaluating a novel in-place metadata scheme for the Deuce framework. This new scheme is based in Java Bytecode transformation techniques and its use requires no changes to the application code. Experimentation indicates that multi-versioning STM algorithms implemented using our new in-place scheme are in average 6 {\texttimes} faster than when implemented with the out-place scheme.

}, keywords = {Automatic configuration, Virtual appliance, Virtualization}, isbn = {978-3-319-14719-2}, issn = {0302-9743}, doi = {10.1007/978-3-319-14720-8_8}, url = {http://dx.doi.org/10.1007/978-3-319-14720-8_8}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/transactional_memory-dias_vale_lourenco.pdf}, author = {Ricardo J. Dias and Vale, Tiago M. and Jo{\~a}o M. Louren{\c c}o}, editor = {Guerraoui, Rachid and Romano, Paolo} } @article {arxiv:2015:dsousa, title = {Preventing Atomicity Violations with Contracts}, journal = {ArXiv e-prints}, year = {2015}, note = {

n/a

}, abstract = {

Software developers are expected to protect concurrent accesses to shared regions of memory with some mutual exclusion primitive that ensures atomicity properties to a sequence of program statements. This approach prevents data races but may fail to provide all necessary correctness properties.The composition of correlated atomic operations without further synchronization may cause atomicity violations. Atomic violations may be avoided by grouping the correlated atomic regions in a single larger atomic scope. Concurrent programs are particularly prone to atomicity violations when they use services provided by third party packages or modules, since the programmer may fail to identify which services are correlated. In this paper we propose to use contracts for concurrency, where the developer of a module writes a set of contract terms that specify which methods are correlated and must be executed in the same atomic scope. These contracts are then used to verify the correctness of the main program with respect to the usage of the module(s). If a contract is well defined and complete, and the main program respects it, then the program is safe from atomicity violations with respect to that module. We also propose a static analysis based methodology to verify contracts for concurrency that we applied to some real-world software packages. The bug we found in Tomcat 6.0 was immediately acknowledged and corrected by its development team.

}, keywords = {and Cluster Computing, Computer Science - Distributed, Computer Science - Programming Languages, Computer Science - Software Engineering, Parallel}, url = {http://arxiv.org/abs/1505.02951}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/1505.02951v1-dsousa.pdf}, author = {Sousa, D. G. and Dias, R. J. and Ferreira, C. and Louren{\c c}o, J. M.} } @conference {icdcn:2015:jsilva, title = {Supporting Multiple Data Replication Models in Distributed Transactional Memory}, booktitle = {Proceedings of the 2015 International Conference on Distributed Computing and Networking}, series = {ICDCN {\textquoteright}15}, year = {2015}, note = {

n/a

}, pages = {11:1{\textendash}11:10}, publisher = {ACM}, organization = {ACM}, address = {Goa, India}, abstract = {

Distributed transactional memory (DTM) presents itself as a highly expressive and programmer friendly model for concurrency control in distributed programming. Current DTM systems make use of both data distribution and replication as a way of providing scalability and fault tolerance, but both techniques have advantages and drawbacks. As such, each one is suitable for different target applications, and deployment environments. In this paper we address the support of different data replication models in DTM. To that end we propose ReDstm, a modular and non-intrusive framework for DTM, that supports multiple data replication models in a general purpose programming language (Java). We show its application in the implementation of distributed software transactional memories with different replication models, and evaluate the framework via a set of well-known benchmarks, analysing the impact of the different replication models on memory usage and transaction throughput.

}, keywords = {Concurrency Control, Data Replication, Distributed Systems, Distributed Transactional Memory}, isbn = {978-1-4503-2928-6}, doi = {10.1145/2684464.2684481}, url = {http://doi.acm.org/10.1145/2684464.2684481}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/icdcn15-jsilva.pdf}, author = {Silva, Jo{\~a}o A. and Vale, Tiago M. and Ricardo J. Dias and Paulino, Herv{\'e} and Jo{\~a}o M. Louren{\c c}o} } @conference {inforum:2014:jsilva, title = {Um Mecanismo de Caching para o Protocolo {SCORe}}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, series = {INForum 2014}, year = {2014}, note = {

n/a

}, month = {sep}, pages = {260{\textendash}275}, publisher = {FEUP Edi{\c c}{\~o}es}, organization = {FEUP Edi{\c c}{\~o}es}, address = {Porto, Portugal}, abstract = {

Os protocolos de replica{\c c}{\~a}o parcial de dados apresentam um grande potencial de escalabilidade. O SCORe {\'e} um protocolo para replica{\c c}{\~a}o parcial proposto recentemente que faz uso de controlo de concorr{\^e}ncia multi-vers{\~a}o. Neste artigo abordamos um dos problemas principais que afeta o desempenho deste tipo de protocolos: a localidade dos dados, i.e., pode-se dar o caso do n{\'o} local n{\~a}o ter uma c{\'o}pia dos dados a que pretende aceder, e nesse caso {\'e} necess{\'a}rio realizar uma ou mais opera{\c c}{\~o}es de leitura remota. Assim, a n{\~a}o ser que se empreguem t{\'e}cnicas para melhorar a localidade no acesso aos dados, o n{\'u}mero de opera{\c c}{\~o}es de leitura remota aumenta com o tamanho do sistema, acabando por afetar o desempenho do mesmo. Nesse sentido, introduzimos um mecanismo de caching que permite replicar c{\'o}pias de dados remotos de maneira a que seja poss{\'{\i}}vel servir localmente dados remotos enquanto que se mant{\'e}m a consist{\^e}ncia dos mesmos e a escalabilidade oferecida pelo protocolo. Avaliamos o mecanismo de caching com um benchmark conhecido da literatura e os resultados experimentais mostram resultados animadores com algum aumento no desempenho do sistema e uma redu{\c c}{\~a}o consider{\'a}vel da quantidade de opera{\c c}{\~o}es de leitura remota.

}, keywords = {Cache, Controlo de concorr{\^e}ncia, Mem{\'o}ria transacional distribu{\'\i}da, Replica{\c c}{\~a}o Parcial de Dados, Sistemas Distribu{\'\i}dos}, isbn = {978-972-752-171-5}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum14-jsilva.pdf}, author = {Silva, Jo{\~a}o A. and Jo{\~a}o M. Louren{\c c}o and Paulino, Herv{\'e}} } @conference {dmtm:2014:lorosa, title = {Hardware Approach for Detecting, Exposing and Tolerating High Level Atomicity Violations}, booktitle = {Proceedings of Joint Euro-TM/MEDIAN Workshop on Dependable Multicore and Transactional Memory Systems}, series = {DMTM 2014}, year = {2014}, note = {

n/a

}, month = {jan}, address = {Vienna, Austria}, abstract = {

In this paper we address a solution for detecting and tolerating one of the most typical concurrency bugs: atomicity violations. More specifically, we address High-Level Atomicity Violations (HLAV). High-level atomicity violations result from the misspecification of the scope of an atomic block, by splitting it in two or more atomic blocks which may be interleaved with other atomic blocks. Figure 1 shows an example of this type of atomicity violation. The intuitive idea behind HLAV is that if two shared data items (e.g., memory locations) were both accessed inside an atomic block, they are interrelated and probably the programmer intention is that there shall be no interleavings between these two accesses. Therefore, if (in the same program) this two addresses are accessed separately in different atomic blocks, an unfortunate interleaving may cause an atomicity violation.

}, url = {http://www.gsd.inesc-id.pt/~mcouceiro/eurotm/dmtm2014/abstracts/orosa.pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/dmtm-2014-lorosa.pdf}, author = {Orosa, Lois and Jo{\~a}o M. Louren{\c c}o} } @conference {dmtm:2014:jsilva, title = {Supporting Partial Data Replication in Distributed Transactional Memory}, booktitle = {Proceedings of Joint Euro-TM/MEDIAN Workshop on Dependable Multicore and Transactional Memory Systems}, series = {DMTM 2014}, year = {2014}, note = {

n/a

}, month = {jan}, address = {Vienna, Austria}, abstract = {

n/a

}, keywords = {Controlo de concorr{\^e}ncia, Java bytecode, Mem{\'o}ria transacional distribu{\'\i}da, Replica{\c c}{\~a}o parcial}, url = {http://www.gsd.inesc-id.pt/~mcouceiro/eurotm/dmtm2014/abstracts/silva.pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/dmtm14-jsilva.pdf}, author = {Silva, Jo{\~a}o A. and Vale, Tiago M. and Ricardo J. Dias and Paulino, Herv{\'e} and Jo{\~a}o M. Louren{\c c}o} } @inbook {memics:2014:jfiedor, title = {On Monitoring C/C++ Transactional Memory Programs}, booktitle = {Mathematical and Engineering Methods in Computer Science}, series = {Lecture Notes in Computer Science}, volume = {8934}, year = {2014}, note = {

n/a

}, pages = {73{\textendash}87}, publisher = {Springer International Publishing}, organization = {Springer International Publishing}, abstract = {

Transactional memory (TM) is an increasingly popular technique for synchronising threads in multi-threaded programs. To address both correctness and performance-related issues of TM programs, one needs to monitor and analyse their execution. However, monitoring concurrent programs (including TM programs) may have a non-negligible impact on their behaviour, which may hamper the objectives of the intended analysis. In this paper, we propose several approaches for monitoring TM programs and study their impact on the behaviour of the monitored programs. The considered approaches range from specialised lightweight monitoring to generic heavyweight monitoring. The implemented monitoring tools are publicly available to the scientific community, and the implementation techniques used for lightweight monitoring of TM programs may be used as an inspiration for developing other specialised lightweight monitors.

}, isbn = {978-3-319-14896-0}, issn = {0302-9743}, doi = {10.1007/978-3-319-14896-0_7}, url = {http://dx.doi.org/10.1007/978-3-319-14896-0_7}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/memics14-monitoring-tm.pdf}, author = {Jan Fiedor and Letko, Zden{\v e}k and Louren{\c c}o, Jo{\~a}o and Vojnar, Tom{\'a}{\v s}}, editor = {Hlin{\v e}n{\'y}, Petr and Dvo{\v r}{\'a}k, Zden{\v e}k and Jaro{\v s}, Ji{\v r}{\'\i} and Kofro{\v n}, Jan and Ko{\v r}enek, Jan and Matula, Petr and Pala, Karel} } @conference {inforum:2013:sousa, title = {Preven{\c c}{\~a}o de Viola{\c c}{\~o}es de Atomicidade usando Contractos}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, series = {INForum 2013}, year = {2013}, note = {

n/a

}, month = {sep}, pages = {190{\textendash}201}, publisher = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, organization = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, address = {Lisbon, Portugal}, abstract = {

A programa{\c c}{\~a}o concorrente obriga o programador a sincronizar os acessos concorrentes a regi{\~o}es de mem{\'o}ria partilhada, contudo esta abordagem n{\~a}o {\'e} suficiente para evitar todas as anomalias que podem ocorrer num cen{\'a}rio concorrente. Executar uma sequ{\^e}ncia de opera{\c c}{\~o}es at{\'o}micas pode causar viola{\c c}{\~o}es de atomicidade se existir uma correla{\c c}{\~a}o entre essas opera{\c c}{\~o}es, devendo o programador garantir que toda a sequ{\^e}ncia de opera{\c c}{\~o}es {\'e} executada atomicamente. Este problema {\'e} especialmente comum quando se usam opera{\c c}{\~o}es de pacotes ou m{\'o}dulos de terceiros, pois o programador pode identificar incorretamente o {\^a}mbito das regi{\~o}es de c{\'o}digo que precisam de ser at{\'o}micas para garantir o correto comportamento do programa. Para evitar este problema o programador do m{\'o}dulo pode criar um contrato que especifica quais as sequ{\^e}ncias de opera{\c c}{\~o}es do m{\'o}dulo que devem ser sempre executadas de forma at{\'o}mica. Este trabalho apresenta uma an{\'a}lise est{\'a}tica para verifica{\c c}{\~a}o destes contratos.

}, keywords = {oral_communication}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum2013-sousa.pdf}, author = {Sousa, Diogo G. and Ferreira, Carla and Jo{\~a}o M. Louren{\c c}o} } @conference {inforum:2013:martins, title = {Replica{\c c}{\~a}o Multi-n{\'\i}vel de Bases de Dados em Mem{\'o}ria}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, series = {INForum 2013}, year = {2013}, note = {

n/a

}, month = {sep}, pages = {190{\textendash}201}, publisher = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, organization = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, address = {Lisbon, Portugal}, abstract = {

Os servi{\c c}os Web s{\~a}o frequentemente suportados por sistemas com uma arquitetura em camadas, sendo utilizadas bases de dados relacionais para armazenamento dos dados. A replica{\c c}{\~a}o dos diversos componentes tem sido uma das formas utilizadas para obter melhorarias de escalabilidade destes servi{\c c}os. Adicionalmente, a utiliza{\c c}{\~a}o de bases de dados em mem{\'o}ria permite alcan{\c c}ar um desempenho mais elevado. No entanto {\'e} conhecida a fraca escalabilidade das bases de dados com o n{\'u}mero de n{\'u}cleos em m{\'a}quinas multi-n{\'u}cleo. Neste artigo propomos uma nova abordagem para lidar com este problema, intitulada MacroDDB. Utilizando uma solu{\c c}{\~a}o de replica{\c c}{\~a}o hier{\'a}rquica, a nossa proposta, replica a base da dados em v{\'a}rios n{\'o}s, sendo que cada n{\'o}, por sua vez, executa um conjunto de r{\'e}plicas da base de dados. Esta abordagem permite assim lidar com a falta de escalabilidade das bases de dados relacionais em m{\'a}quinas multi-n{\'u}cleo, o que por sua vez melhora a escalabilidade geral dos servi{\c c}os.

}, keywords = {oral_communication}, isbn = {978-989-97060-8-8}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum2013-martins.pdf}, author = {Martins, Helder R. L. and Soares, Jo{\~a}o and Jo{\~a}o M. Louren{\c c}o and Pregui{\c c}a, Nuno} } @article {CPE3098:2013:dias, title = {Efficient support for in-place metadata in Java software transactional memory}, journal = {Concurrency and Computation: Practice and Experience}, volume = {25}, number = {17}, year = {2013}, note = {

n/a

}, pages = {2394{\textendash}2411}, abstract = {

Software transactional memory (STM) algorithms associate metadata with the memory locations accessed during a transaction{\textquoteright}s lifetime. This metadata may be stored in an external table by resorting to a mapping function that associates the address of a memory cell with the table entry containing the corresponding metadata (out-place or external strategy). Alternatively, the metadata may be stored adjacent to the associated memory cell by wrapping the cell and metadata together (in-place strategy). The implementation techniques to support these two approaches are very different and each STM framework is usually biased towards one of them, only allowing the efficient implementation of STM algorithms which suit one of the approaches and inhibiting a fair comparison with STM algorithms suiting the other. In this paper, we introduce a technique to implement in-place metadata that does not wrap memory cells, thus overcoming the bias and allowing STM algorithms to directly access the transactional metadata. The proposed technique is available as an extension to Deuce and enables the efficient implementation of a wide range of STM algorithms and their fair (unbiased) comparison in a common STM framework. We illustrate the benefits of our approach by analyzing its impact in two popular transactional memory algorithms with several transactional workloads, TL2 and multiversioning, each befitting out-place and in-place, respectively.

}, keywords = {bytecode instrumentation, data structures, Java, software transactional memory}, issn = {1532-0634}, doi = {10.1002/cpe.3098}, url = {http://dx.doi.org/10.1002/cpe.3098}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/ccpe2013-dias.pdf}, author = {Ricardo J. Dias and Vale, Tiago M. and Jo{\~a}o M. Louren{\c c}o} } @inbook {europar:2013:soares, title = {MacroDB: Scaling Database Engines on Multicores}, booktitle = {Euro-Par 2013 Parallel Processing}, series = {Lecture Notes in Computer Science}, volume = {8097}, year = {2013}, note = {

n/a

}, pages = {607-619}, publisher = {Springer Berlin Heidelberg}, organization = {Springer Berlin Heidelberg}, abstract = {

n/a

}, isbn = {978-3-642-40046-9}, doi = {10.1007/978-3-642-40047-6_61}, url = {http://dx.doi.org/10.1007/978-3-642-40047-6_61}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/europar2013-soares.pdf}, author = {Soares, Jo{\~a}o and Jo{\~a}o M. Louren{\c c}o and Pregui{\c c}a, Nuno}, editor = {Wolf, Felix and Mohr, Bernd and Mey, Dieter} } @proceedings {musepat:2013:proceedings, title = {Multicore Software Engineering, Performance, and Tools}, journal = {Proceedings of the 2nd International Conference on Multicore Software Engineering, Performance, and Tools, MUSEPAT 2013, Saint Petersburg, Russia, August 19{\textendash}20, 2013}, volume = {8063}, year = {2013}, note = {

n/a

}, publisher = {Springer Berlin Heidelberg}, abstract = {

n/a

}, isbn = {978-3-642-39954-1}, issn = {0302-9743}, doi = {10.1007/978-3-642-39955-8}, url = {http://dx.doi.org/10.1007/978-3-642-39955-8}, author = {Jo{\~a}o M. Louren{\c c}o and Farchi, Eitan}, editor = {Jo{\~a}o M. Louren{\c c}o and Farchi, Eitan} } @inbook {musepat:2013:vale, title = {On the Relevance of Total-Order Broadcast Implementations in Replicated Software Transactional Memories}, booktitle = {Multicore Software Engineering, Performance, and Tools}, series = {Lecture Notes in Computer Science}, volume = {8063}, year = {2013}, note = {

n/a

}, pages = {49-60}, publisher = {Springer Berlin Heidelberg}, organization = {Springer Berlin Heidelberg}, abstract = {

n/a

}, isbn = {978-3-642-39954-1}, doi = {10.1007/978-3-642-39955-8_5}, url = {http://dx.doi.org/10.1007/978-3-642-39955-8_5}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/musepat13-vale.pdf}, author = {Vale, Tiago M. and Ricardo J. Dias and Jo{\~a}o M. Louren{\c c}o}, editor = {Jo{\~a}o M. Louren{\c c}o and Farchi, Eitan} } @conference {inforum:2013:silva, title = {Replica{\c c}{\~a}o Parcial com Mem{\'o}ria Transacional Distribu{\'\i}da}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, series = {INForum 2013}, year = {2013}, note = {

n/a

}, pages = {310{\textendash}321}, publisher = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, organization = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, address = {Lisbon, Portugal}, abstract = {

Os sistemas de mem{\'o}ria transacional distribu{\'\i}da atuais recorrem essencialmente {\`a} distribui{\c c}{\~a}o ou {\`a} replica{\c c}{\~a}o total para distribuir os seus dados pelos m{\'u}ltiplos n{\'o}s do sistema. No entanto, estas estrat{\'e}gias de replica{\c c}{\~a}o de dados apresentam limita{\c c}{\~o}es. A distribui{\c c}{\~a}o n{\~a}o oferece toler{\^a}ncia a falhas e a replica{\c c}{\~a}o total limita a capacidade de armazenamento do sistema. Nesse contexto, a replica{\c c}{\~a}o parcial de dados surge como uma solu{\c c}{\~a}o interm{\'e}dia, que combina o melhor das duas anteriores com o intuito de mitigar as suas desvantagens. Esta estrat{\'e}gia tem sido explorada no contexto das bases de dados distribu{\'\i}das, mas tem sido pouco abordada no contexto da mem{\'o}ria transacional e, tanto quanto sabemos, nunca antes tinha sido incorporada num sistema de mem{\'o}ria transacional distribu{\'\i}da para uma linguagem de prop{\'o}sito geral. Assim, neste artigo propomos e avaliamos uma infraestrutura para replica{\c c}{\~a}o parcial de dados para programas Java bytecode, que foi desenvolvida com base num sistema j{\'a} existente de mem{\'o}ria transacional distribu{\'\i}da. A modularidade da infraestrutura que apresentamos permite a implementa{\c c}{\~a}o de m{\'u}ltiplos algoritmos e, por conseguinte, avaliar em que contextos de utiliza{\c c}{\~a}o (workloads, n{\'u}mero de n{\'o}s, etc.) a replica{\c c}{\~a}o parcial se apresenta como uma alternativa vi{\'a}vel a outras estrat{\'e}gias de replica{\c c}{\~a}o de dados.

}, keywords = {Controlo de concorr{\^e}ncia, Java bytecode, Mem{\'o}ria transacional distribu{\'\i}da, Replica{\c c}{\~a}o parcial}, isbn = {978-989-97060-8-8}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum13-silva.pdf}, author = {Silva, Jo{\~a}o A. and Vale, Tiago M. and Jo{\~a}o M. Louren{\c c}o and Paulino, Herv{\'e}} } @conference {ewdc:soares:2013, title = {Software Component Replication for Improved Fault-Tolerance: Can Multicore Processors Make It Work?}, booktitle = {Dependable Computing}, series = {Lecture Notes in Computer Science}, volume = {7869}, year = {2013}, note = {

n/a

}, pages = {173-180}, publisher = {Springer Berlin Heidelberg}, organization = {Springer Berlin Heidelberg}, abstract = {

n/a

}, isbn = {978-3-642-38788-3}, doi = {10.1007/978-3-642-38789-0_15}, url = {http://dx.doi.org/10.1007/978-3-642-38789-0_15}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/ewdc2013.pdf}, author = {Soares, Jo{\~a}o and Jo{\~a}o M. Louren{\c c}o and Pregui{\c c}a, Nuno}, editor = {Vieira, Marco and Cunha, Jo{\~a}oCarlos} } @conference {pessanha:2012:hvc, title = {Precise Detection of Atomicity Violations}, booktitle = {Haifa Verification Conference}, series = {Lecture Notes in Computer Science}, year = {2012}, note = {

Best Paper Award

}, month = {Nov 2012}, publisher = {Springer Berlin / Heidelberg}, organization = {Springer Berlin / Heidelberg}, address = {Haifa, Israel}, abstract = {

Concurrent programs that are free of unsynchronized ac- cesses to shared data may still exhibit unpredictable concurrency errors called atomicity violations, which include both high-level dataraces and stale-value errors. Atomicity violations occur when programmers make wrong assumptions about the atomicity scope of a code block, incorrectly splitting it in two or more atomic blocks and allow them to be interleaved with other atomic blocks. In this paper we propose a novel static analysis algorithm that works on a dependency graph of program variables and detects both high-level dataraces and stale-value errors. The algorithm was implemented for a Java Bytecode analyzer and its effectiveness was evaluated with some well known faulty programs. The results obtained show that our algorithm performs better than previous approaches, achieving higher precision for small and medium sized programs, making it a good basis for a practical tool.

}, issn = {0302-9743}, url = {http://www.research.ibm.com/haifa/conferences/hvc2012/}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/hvc2012.pdf}, author = {Ricardo J. Dias and Pessanha, Vasco and Jo{\~a}o M. Louren{\c c}o} } @conference {vale:2012:inforum, title = {Uma Infraestrutura para Suporte de Mem{\'o}ria Transacional Distribu{\'\i}da}, booktitle = {INForum 2012: Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, year = {2012}, note = {

n/a

}, month = {7 Sep.}, publisher = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, organization = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, address = {Monte de Capraica, PT}, abstract = {

As t{\'e}cnicas e algoritmos desenvolvidos sobre diferentes infraestruturas espec{\'\i}ficas dificilmente podem ser comparados entre si. Este princ{\'\i}pio tamb{\'e}m se aplica {\`a}s infraestruturas para execu{\c c}{\~a}o de Mem{\'o}ria Transacional Distribu{\'\i}da (MTD), pois n{\~a}o s{\'o} s{\~a}o muito escassas aquelas que permitem o desenvolvimento, teste e compara{\c c}{\~a}o de v{\'a}rios algoritmos e t{\'e}cnicas de implementa{\c c}{\~a}o, como fornecem uma interface intrusiva para o programador. Sem uma compara{\c c}{\~a}o justa, n{\~a}o {\'e} poss{\'\i}vel aferir quais as t{\'e}cnicas e algoritmos mais apropriados em cada contexto de utiliza{\c c}{\~a}o (workload). Neste artigo propomos uma infraestrutura generalista, muito flex{\'\i}vel, que possibilita a experimenta{\c c}{\~a}o de v{\'a}rias estrat{\'e}gias de MTD, permitindo o desenvolvimento de uma grande variedade de algoritmos e de t{\'e}cnicas de implementa{\c c}{\~a}o eficientes e otimizadas. Atrav{\'e}s da sua utiliza{\c c}{\~a}o, {\'e} agora poss{\'\i}vel a compara{\c c}{\~a}o de t{\'e}cnicas e algoritmos em diferentes contextos de utiliza{\c c}{\~a}o (workloads), recorrendo a uma {\'u}nica infraestrutura e com implica{\c c}{\~o}es m{\'\i}nimas no c{\'o}digo da aplica{\c c}{\~a}o.

}, isbn = {978-972-8893-32-3}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum-dstm.pdf}, author = {Vale, Tiago M. and Ricardo J. Dias and Jo{\~a}o M. Louren{\c c}o} } @conference {Sousa:2012:inforum, title = {Aplica{\c c}{\~a}o do Fecho de Programas na Dete{\c c}{\~a}o de Anomalias de Concorr{\^e}ncia}, booktitle = {INForum 2012: Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica}, year = {2012}, note = {

n/a

}, month = {6 Sep.}, publisher = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, organization = {Faculdade de Ci{\^e}ncias e Tecnologia da Universidade Nova de Lisboa}, address = {Monte de Caparica, PT}, abstract = {

Uma das estrat{\'e}gias para tirar partido dos m{\'u}ltiplos processadores dispon{\'\i}veis nos computadores atuais passa por adaptar c{\'o}digo legado, inicialmente concebido para ser executado num contexto meramente sequencial, para ser agora executado num contexto multithreading. Nesse processo de adapta{\c c}{\~a}o {\'e} necess{\'a}rio proteger apropriadamente os dados que s{\~a}o agora partilhados e acedidos por diferentes threads concorrentes. A prote{\c c}{\~a}o dos dados com locks usando uma granulosidade grossa inibe a concorr{\^e}ncia e op{\~o}e-se ao objetivo inicial de explorar o paralelismo suportado por m{\'u}ltiplos processadores. Por outro lado, a utiliza{\c c}{\~a}o de uma granulosidade fina pode levar {\`a} ocorr{\^e}ncia de anomalias pr{\'o}prias da concorr{\^e}ncia, como deadlocks e viola{\c c}{\~o}es de atomicidade (high-level data races). Este artigo discute o conceito de fecho de um programa e uma metodologia que, quando aplicados em conjunto, permitem adaptar c{\'o}digo legado para o tornar thread-safe, garantindo a aus{\^e}ncia de viola{\c c}{\~o}es de atomicidade na vers{\~a}o corrente do software e antecipando algumas viola{\c c}{\~o}es de atomicidade que poder{\~a}o ocorrer em vers{\~o}es futuras do mesmo software.

}, isbn = {978-972-8893-32-3" pages = {190{\textendash}201}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum-closure.pdf}, author = {Sousa, Diogo G. and and Louren{\c c}o, Jo{\~a}o M. and Farchi, Eitan and Segall, Itai} } @conference {2875, title = {Verification of Snapshot Isolation in Transactional Memory Java Programs}, booktitle = {Proceedings of the 26th European Conference on Object-Oriented Programming}, series = {{ECOOP}}, year = {2012}, note = {

n/a

}, month = {11-16 June}, address = {Beijing, China}, abstract = {

This paper presents an automatic verification technique for transactional memory Java programs executing under snapshot isolation level. We certify which transactions in a program are safe to execute under snapshot isolation without triggering the write-skew anomaly, opening the way to run-time optimizations that may lead to considerable performance enhancements. Our work builds on a novel deep-heap analysis technique based on separation logic to statically approximate the read- and write-sets of a transactional memory Java program. We implement our technique and apply our tool to a set of micro benchmarks and also to one benchmark of the STAMP package. We corroborate known results, certifying some of the examples for safe execution under snapshot isolation by proving the absence of write-skew anomalies. In other cases our analysis has identified transactions that potentially trigger previously unknown write-skew anomalies.\>

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/ecoop12.pdf}, author = {Ricardo Jorge Dias and Dino Distefano and Jo{\~a}o Costa Seco and Jo{\~a}o Manuel Louren{\c c}o} } @conference {europar-dias:2012, title = {Efficient Support for In-Place Metadata in Transactional Memory}, booktitle = {Proceedings of the 18th International Euro-Par Conference on Parallel Processing}, series = {{Euro-Par}}, year = {2012}, note = {

Distinguished paper award

}, publisher = {Springer-Verlag}, organization = {Springer-Verlag}, address = {Berlin, Heidelberg}, abstract = {

Software Transactional Memory (STM) algorithms correctness rely on metadata associated with the memory locations accessed during the transaction life-time. STM implementations may store this metadata either in-place, by wrapping the memory cells in a container that includes the memory cell itself and the corresponding metadata, or out-place, by resorting to a mapping function that associates the memory cell address to an external table with the corresponding metadata. The implementation techniques for these two approaches are very different and each STM framework is usually biased towards one of them, only allowing the efficient implementation of algorithms that fall into the appropriate category, and inhibiting the fair comparison with STM algorithms falling into the other. In this paper we introduce a technique that supports the use of in-place metadata without requiring to wrap memory cells, thus providing STM algorithms with direct access to the transactional metadata and overcoming the bias. The proposed technique is available as an extension to the DeuceSTM framework and allows the efficient implementation of a wide range of STM algorithms, thus enabling their fair (unbiased) comparison in a common STM infrastructure. We illustrate the benefits of our approach by analyzing its impact in two popular TM algorithms with two different transactional workloads, TL2 and multi-versioning, which bias to out-place and in-place respectively.

}, url = {http://dx.doi.org/10.1007/978-3-642-32820-6_59}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/europar12.pdf}, author = {Ricardo J. Dias and Vale, Tiago M. and Jo{\~a}o M. Louren{\c c}o} } @conference {padtad-farchi:2012, title = {Using Program Closures to Make an Application Programming Interface (API) Implementation Thread Safe}, booktitle = {PADTAD{\textquoteright}12: Proceedings of the 10th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging}, series = {PADTAD}, year = {2012}, note = {

n/a

}, publisher = {ACM}, organization = {ACM}, address = {Minneapolis, MN, USA}, abstract = {

A set of methods defining an API (Application Programming Interface) are to be made thread safe; thus running any subset of these methods in parallel should not create races or deadlocks. Originally, the set of methods were not designed to be thread safe, so races and deadlocks are expected when running them in parallel. The number of possible interleavings when running methods from this API in parallel is huge, and this work focuses on the identification of the high level data races introduced by such interleavings. We propose an analysis that avoids the exhaustive exploration of all possible interleavings. For a concurrent program P, the closure of P, clos(P), is defined. Roughly speaking, we can say that the clos(P) is obtained by adding threads to P in such a way that high level data races resulting from running P in parallel to other programs are exposed statically. A set of methods representing the API is then modeled as a set of concurrent programs and their closure is analysed to identify high level data races. These high level data races are then inspected and removed to make the API thread safe. We illustrate the application of this methodology with a simple use case.

}, keywords = {concurrency, software transactional memory, static analysis, testing, verification}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/programclosure.pdf}, author = {Farchi, Eitan and Segall, Itai and Jo{\~a}o M. Louren{\c c}o and Sousa, Diogo} } @conference {dias-hotpar-2011, title = {Efficient and Correct Transactional Memory Programs Combining Snapshot Isolation and Static Analysis}, booktitle = {Proceedings of the 3rd USENIX Conference on Hot Topics in Parallelism (HotPar{\textquoteright}11)}, series = {{HotPar}{\textquoteright}11}, year = {2011}, note = {

n/a

}, month = {May}, publisher = {Usenix Association}, organization = {Usenix Association}, address = {Berkeley, USA}, abstract = {

Concurrent programs may suffer from concurrency anomalies that may lead to erroneous and unpredictable program behaviors. To ensure program correctness, these anomalies must be diagnosed and corrected. This paper addresses the detection of both low- and high-level anomalies in the Transactional Memory setting. We propose a static analysis procedure and a framework to address Transactional Memory anomalies. We start by dealing with the classic case of low-level dataraces, identifying concurrent accesses to shared memory cells that are not protected within the scope of a memory transaction. Then, we address the case of high-level dataraces, bringing the programmer{\textquoteright}s attention to pairs of memory transactions that were misspecified and should have been combined into a single transaction. Our framework was applied to a set of programs, collected form different sources, containing well known low- and high-level anomalies. The framework demonstrated to be accurate, confirming the effectiveness of using static analysis techniques to precisely identify concurrency anomalies in Transactional Memory programs.

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/hotpar2011.pdf}, author = {Ricardo J. Dias and Jo{\~a}o M. Louren{\c c}o and Pregui{\c c}a, Nuno} } @conference {Pessanha:2011:PVH:2002962.2002968, title = {Practical verification of high-level dataraces in transactional memory programs}, booktitle = {Proceedings of 9th the Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging}, series = {PADTAD{\textquoteright}11}, year = {2011}, month = {July}, pages = {26{\textendash}34}, publisher = {ACM}, organization = {ACM}, address = {New York, NY, USA}, abstract = {

In this paper we present MoTh, a tool that uses static analysis to enable the automatic verification of concurrency anomalies in Transactional Memory Java programs. Currently MoTh detects high-level dataraces and stale-value errors, but it is extendable by plugging-in sensors, each sensor implementing an anomaly detecting algorithm. We validate and benchmark MoTh by applying it to a set of well known concurrent buggy programs and by close comparison of the results with other similar tools. The results achieved so far are very promising, yielding good accuracy while triggering only a very limited number of false warnings.

}, keywords = {concurrency, software transactional memory, static analysis, testing, verification}, isbn = {9781-450-3080-9-0}, doi = {http://doi.acm.org/10.1145/2002962.2002968}, url = {http://doi.acm.org/10.1145/2002962.2002968}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/isstaws11padtad-4-pessanha.pdf}, author = {Pessanha, Vasco and Ricardo J. Dias and Jo{\~a}o M. Louren{\c c}o and Farchi, Eitan and Sousa, Diogo} } @conference {oliveira:2011:inforum, title = {Acelera{\c c}{\~a}o de Computa{\c c}{\~o}es Cient{\'\i}ficas com Processadores Heterog{\'e}neos}, booktitle = {InForum 2011: Proceedings of InForum Simp{\'o}sio de Inform{\'a}tica}, year = {2011}, note = {

n/a

}, publisher = {Universidade do Coimbra}, organization = {Universidade do Coimbra}, address = {Coimbra}, abstract = {

Actualmente o mercado residencial de computadores inclui n{\~a}o s{\'o} multiprocessadores com diversos n{\'u}cleos (CPUs) como tamb{\'e}m placas gr{\'a}ficas (GPUs) cuja capacidade de processamento tem evolu{\'\i}do a um ritmo exponencial. Este poder computacional pode ser utilizado para outros fins para al{\'e}m do processamento gr{\'a}fico, tal como o processamento de algoritmos comuns em computa{\c c}{\~a}o cient{\'\i}fica. Neste artigo {\'e} apresentada, discutida e avaliada a framework Cheetah, uma framework que distribui programas computacionalmente exigentes sobre uma rede de CPUs e GPUs. Um programador que utilize a Cheetah apenas necessita de especificar o seu programa como um conjunto de kernels OpenCL, relegando para a framework a distribui{\c c}{\~a}o destes pelas unidades de processamento dispon{\'\i}veis. O programa pode assim escalar {\`a} medida que s{\~a}o adicionados novos recursos computacionais, sem quaisquer esfor{\c c}os adicionais de adapta{\c c}{\~a}o ou recompila{\c c}{\~a}o. Os testes realizados demonstraram a capacidade de a framework providenciar acelerac{\c c}{\~o}s at{\'e} duas ordens de grandeza com um esfor{\c c}o de desenvolvimento reduzido, mesmo quando na presen{\c c}a de recursos computacionais limitados.

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum-pitxyoki.pdf}, author = {Oliveira, Lu{\'\i}s Picciochi and Jo{\~a}o M. Louren{\c c}o} } @article {DBLP:journals/comsis/LouSTD11, title = {Detecting concurrency anomalies in transactional memory programs}, journal = {Comput. Sci. Inf. Syst.}, volume = {8}, number = {2}, year = {2011}, note = {

n/a

}, pages = {533{\textendash}548}, abstract = {

Software transactional memory is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to main memory (RAM). This paper discusses how to support revertible operations, such as memory allocation and release, within software libraries that will be used in software memory transactional contexts. The proposal is based in the extension of the transaction life cycle state diagram with new states associated to the execution of user-defined handlers. The proposed approach is evaluated in terms of functionality and performance by way of a use case study and performance tests. Results demonstrate that the proposal and its current implementation are flexible, generic and efficient

}, keywords = {compensation actions, revertible operations, software transactional memory, transactions}, doi = {10.2298/CSIS110110007L}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/comsis-2011.pdf}, author = {Louren{\c c}o, Jo{\~a}o and Sousa, Diogo and Teixeira, Bruno C. and Ricardo J. Dias} } @booklet {DLS2011, title = {Detection of Snapshot Isolation Anomalies in Software Transactional Memory: A Statical Analysis Approach}, number = {UNL-DI-5-2011}, year = {2011}, note = {

n/a

}, publisher = {Departamento de Inform{\'a}tica FCT/UNL}, abstract = {

n/a

}, author = {Ricardo J. Dias and Jo{\~a}o M. Louren{\c c}o and Jo{\~a}o Costa Seco} } @proceedings {hvc:2011:proceedings, title = {Hardware and Software: Verification and Testing}, journal = {Haifa Verification Conference}, year = {2011}, note = {

n/a

}, publisher = {Springer Berlin / Heidelberg}, address = {Haifa, Israel}, abstract = {

n/a

}, author = {Eder, Kerstin and Jo{\~a}o M. Louren{\c c}o and Onn Shehory}, editor = {Eder, Kerstin and Jo{\~a}o M. Louren{\c c}o and and Shehory, Onn} } @proceedings {Lourenco:2011:2002962, title = {Proceedings of the 9th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging (PADTAD{\textquoteright}11)}, year = {2011}, note = {

n/a

}, publisher = {ACM}, address = {New York, NY, USA}, abstract = {

n/a

}, isbn = {9781-450-3080-9-0}, author = {Jo{\~a}o M. Louren{\c c}o and Farchi, Eitan and Ur, Shmuel}, editor = {Jo{\~a}o M. Louren{\c c}o and Farhi, Eitan and Ur, Shmuel} } @inbook {springerlink:10.1007/978-3-642-19583-9_7, title = {Special Session on Debugging}, booktitle = {Hardware and Software: Verification and Testing}, series = {Lecture Notes in Computer Science}, volume = {6504}, year = {2011}, note = {

n/a

}, pages = {24{\textendash}28}, publisher = {Springer Berlin / Heidelberg}, organization = {Springer Berlin / Heidelberg}, abstract = {

In software, hardware, and embedded system domains, debugging is the process of locating and correcting faults in a system. Depending on the context, the various characteristics of debugging induce different challenges and solutions. Post-silicon hardware debugging, for example, needs to address issues such as limited visibility and controllability, while debugging software entails other issues, such as the handling of distributed or non-deterministic computation. The challenges that accompany such issues are the focus of many current research efforts. Solutions for debugging range from interactive tools to highly analytic techniques. We have seen great advances in debugging technologies in recent years, but bugs continue to occur, and debugging still encompasses significant portions of the life-cycles of many systems. The session covered state-of-the-art approaches as well as promising new research directions in both the hardware and software domains.

}, issn = {0302-9743}, doi = {10.1007/978-3-642-19583-9_7}, url = {http://dx.doi.org/10.1007/978-3-642-19583-9_7}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/hvc2010-secial_session_on_debugging.pdf}, author = {Hollander, Yoav and Hu, Alan and Jo{\~a}o M. Louren{\c c}o and Morad, Ronny}, editor = {Barner, Sharon and Harris, Ian and Kroening, Daniel and Raz, Orna} } @booklet {DDLS2011, title = {StarTM: Automatic Verification of Snapshot Isolation in Transactional Memory Java Programs}, number = {UNL-DI-6-2011}, year = {2011}, note = {

n/a

}, publisher = {Departamento de Inform{\'a}tica FCT/UNL}, abstract = {

This paper presents StarTM , an automatic verification tool for transactional memory Java programs executing under relaxed isolation levels. We certify which transactions in a program are safe to execute under Snapshot Isolation without triggering the write-skew anomaly, opening the way to run-time optimizations that may lead to considerable performance enhancements.
Our tool builds on a novel shape analysis technique based on Separation Logic to statically approximate the read- and write-sets of a transactional memory Java program. This technique is particularly challenging due to the presence of dynamically allocated memory.
We implement our technique and apply our tool to a set of intricate examples. We corroborate known results, certifying some of the examples for safe execution under Snapshot Isolation by proving the absence of write-skew anomalies. In other cases we identify transactions that potentially trigger the write-skew anomaly.

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/ddls11.pdf}, author = {Ricardo J. Dias and Dino Distefano and Jo{\~a}o M. Louren{\c c}o and Jo{\~a}o Costa Seco} } @conference {luis:2011:inforum, title = {Suporte Transaccional para o Sistema de Ficheiros Btrfs}, booktitle = {InForum 2011: Proceedings of InForum Simp{\'o}sio de Inform{\'a}tica}, year = {2011}, note = {

n/a

}, publisher = {Universidade do Coimbra}, organization = {Universidade do Coimbra}, address = {Coimbra}, abstract = {

Em caso de falha abrupta de um sistema, {\'e} imperativo garantir a consist{\^e}ncia do Sistema de Ficheiros (SF). Actualmente existem v{\'a}rias solu{\c c}{\~o}es que visam garantir que tanto os dados como os metadados do SF se encontram num estado consistente, mas que n{\~a}o contemplam a garantia de consist{\^e}ncia dos dados do ponto de vista das aplica{\c c}{\~o}es. Por exemplo, aplica{\c c}{\~o}es que pretendam alterar v{\'a}rios ficheiros de configura{\c c}{\~a}o ter{\~a}o de encontrar mecanismos para garantir que, ou todos os ficheiros s{\~a}o devidamente alterados, ou nenhum o {\'e}, evitando assim que numa situa{\c c}{\~a}o de falha o conte{\'u}do dos ficheiros fique inconsistente. Do ponto de vista da aplica{\c c}{\~a}o, pode n{\~a}o ser simples implementar este comportamento sobre um SF t{\'\i}pico; e pode tamb{\'e}m n{\~a}o ser razo{\'a}vel utilizar um Sistema de Gest{\~a}o de Bases de Dados (SGBD), que oferece propriedades ACID. Neste artigo propomos, testamos e avaliamos uma integra{\c c}{\~a}o das propriedades ACID num SF. Partindo do suporte para snapshots do sistema de ficheiros Btrfs, oferece-se uma sem{\^a}ntica transaccional {\`a}s aplica{\c c}{\~o}es que operam sobre volumes (sub-{\'a}rvores) do SF, sem comprometer a sem{\^a}ntica POSIX do SF.

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum-txbtrfs-short.pdf , https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/inforum-txbtrfs-full.pdf}, author = {Lu{\'\i}s, Jo{\~a}o E. and Jo{\~a}o M. Louren{\c c}o and Lopes, Paulo A.} } @inbook {springerlink:10.1007/978-3-642-19583-9_1, title = {Understanding Transactional Memory (Extended Abstract)}, booktitle = {Hardware and Software: Verification and Testing}, series = {Lecture Notes in Computer Science}, volume = {6504}, year = {2011}, note = {

n/a

}, pages = {1{\textendash}2}, publisher = {Springer Berlin / Heidelberg}, organization = {Springer Berlin / Heidelberg}, abstract = {

Transactional Memory [3] (TM) is a new paradigm for concurrency control that brings the concept of transactions, widely known from the Databases community, into the management of data located in main memory. TM delivers a powerful semantics for constraining concurrency and provides the means for the extensive use of the available parallel hardware. TM uses abstractions that promise to ease the development of scalable parallel applications by achieving performances close to fine-grained locking while maintaining the simplicity of coarse-grained locking.

}, issn = {0302-9743}, doi = {10.1007/978-3-642-19583-9_1}, url = {http://dx.doi.org/10.1007/978-3-642-19583-9_1}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/hvc2010-understanding_transactional_memory.pdf}, author = {Jo{\~a}o M. Louren{\c c}o}, editor = {Barner, Sharon and Harris, Ian and Kroening, Daniel and Raz, Orna} } @conference {Teixeira:2010:DTM:1866210.1866213, title = {Detection of Transactional Memory Anomalies using Static Analysis}, booktitle = {Proceedings of the 8th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging (PADTAD{\textquoteright}10)}, series = {{PADTAD}{\textquoteright}10}, year = {2010}, pages = {26{\textendash}36}, publisher = {ACM}, organization = {ACM}, address = {New York, NY, USA}, abstract = {

Transactional Memory allows programmers to reduce the number of synchronization errors introduced in concurrent programs, but does not ensures its complete elimination. This paper proposes a pattern matching based approach to the static detection of atomicity violation, based on a path-sensitive symbolic execution method to model four anomalies that may affect Transactional Memory programs. The proposed technique may be used to to bring to programmer{\textquoteright}s attention pairs of transactions that the programmer has mis-specified, and should have been combined into a single transaction. The algorithm first traverses the AST tree, removing all the non-transactional blocks and generating a trace tree in the path sensitive manner for each thread. The trace tree is a Trie like data structure, where each path from root to a leaf is a list of transactions. For each pair of threads, erroneous patterns involving two consecutive transactions are then checked in the trace tree. Results allow to conclude that the proposed technique, although triggering a moderate number of false positives, can be successfully applied to Java programs, correctly identifying the vast majority of the relevant erroneous patterns.

}, keywords = {concurrency, software transactional memory, static analysis, testing, verification}, isbn = {9781-450-3013-6-7}, doi = {10.1145/1866210.1866213}, url = {http://doi.acm.org/10.1145/1866210.1866213}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/p3-teixeira.pdf}, author = {Teixeira, Bruno and Jo{\~a}o M. Louren{\c c}o and Farchi, Eitan and Ricardo J. Dias and Sousa, Diogo} } @conference {duro:2010:DTM:1866210.1866217, title = {Open Virtualization Framework for Testing Ground Systems}, booktitle = {Proceedings of the 8th Workshop on Parallel and Distributed Systems (PADTAD{\textquoteright}10)}, year = {2010}, pages = {67{\textendash}73}, publisher = {ACM}, organization = {ACM}, address = {New York, NY, USA}, abstract = {

The recent developments in virtualization change completely the panorama of the Hardware/OS deployment. New bottlenecks arise in the deployment of application stacks, where IT industry will spend most of the time to assure automation. VIRTU tool aims at managing, configuring and testing distributed ground applications of space systems on a virtualized environment, based on open tools and cross virtualization support. This tool is a spin-off of previous activities performed by the European Space Operations Center (ESOC) and thus it covers the original needs from the ground data systems infrastructure division of the European Space Agency. VIRTU is a testing oriented solution. Its ability to group several virtual machines in an assembly provides the means to easily deploy a full testing infrastructure, including the client/server relationships. The possibility of making on-demand request of the testing infrastructure will provide some infrastructure optimizations, specially having in mind that ESA maintains Ground Control software of various missions, and each mission cam potentially have a different set of System baselines and last up to 15 years. The matrix array of supported system combinations is therefore enormous and any improvement on the process provides substantial benefits to ESA, by reducing the effort and schedule of each maintenance activity. The ESOC{\textquoteright}s case study focuses on the development and validation activities of infrastructure or mission Ground Systems solutions. The Ground Systems solutions are typically composed of distributed systems that could take advantage of virtualized environments for testing purposes. Virtualization is used as way to optimize maintenance for tasks such as testing new releases and patches, test different system{\textquoteright}s configurations and replicate tests. The main benefits identified are related to deployment test environment and the possibility to have on-demand infrastructure.

}, isbn = {9781-450-3013-6-7}, doi = {10.1145/1866210.1866217}, url = {http://dx.doi.org/10.1145/1866210.1866217}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/p7-duro.pdf}, author = {Duro, Nuno and Santos, Rui and Jo{\~a}o M. Louren{\c c}o and Paulino, Herv{\'e} and Martins, Jo{\~a}o} } @proceedings {Lourenco:2010:1866210, title = {Proceedings of the 8th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging (PADTAD{\textquoteright}10)}, year = {2010}, note = {

n/a

}, publisher = {ACM}, address = {New York, NY, USA}, abstract = {

n/a

}, isbn = {9781-450-3013-6-7}, author = {Jo{\~a}o M. Louren{\c c}o and Farchi, Eitan and Ur, Shmuel}, editor = {Jo{\~a}o M. Louren{\c c}o and Farhi, Eitan and Ur, Shmuel} } @inbook {springerlink:10.1007/978-3-642-15654-0_5, title = {SmART: An Application Reconfiguration Framework}, booktitle = {Complex Systems Design \& Management}, year = {2010}, note = {

n/a

}, pages = {73{\textendash}84}, publisher = {Springer Berlin Heidelberg}, organization = {Springer Berlin Heidelberg}, abstract = {

SmART (Smart Application Reconfiguration Tool) is a framework for the automatic configuration of systems and applications. The tool implements an application configuration workflow that resorts to the similarities between configuration files (i.e., patterns such as parameters, comments and blocks) to allow a syntax independent manipulation and transformation of system and application configuration files.Without compromising its generality, SmART targets virtualized IT infrastructures, configuring virtual appliances and its applications. SmART reduces the time required to (re)configure a set of applications by automating time-consuming steps of the process, independently of the nature of the application to be configured. Industrial experimentation and utilization of SmART show that the framework is able to correctly transform a large amount of configuration files into a generic syntax and back to their original syntax. They also show that the elapsed time in that process is adequate to what would be expected of an interactive tool. SmART is currently being integrated into the VIRTU bundle, whose trial version is available for download from the projects web page.

}, keywords = {Automatic configuration, Virtual appliance, Virtualization}, isbn = {978-3-642-15654-0}, doi = {10.1007/978-3-642-15654-0_5}, url = {http://dx.doi.org/10.1007/978-3-642-15654-0_5}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/csdm.pdf}, author = {Paulino, Herv{\'e} and Martins, Jo{\~a}o Andr{\'e} and Jo{\~a}o M. Louren{\c c}o and Duro, Nuno}, editor = {Aiguier, Marc and Bretaudeau, Francis and Krob, Daniel} } @conference {dias10_inforum, title = {Snapshot Isolation Anomalies Detection in Software Transactional Memory}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica (InForum 2010)}, year = {2010}, note = {

n/a

}, publisher = {Universidade do Minho}, organization = {Universidade do Minho}, address = {Braga, Portugal}, abstract = {

Some performance issues of transactional memory are caused by unnecessary abort situations where non serializable and yet non conflicting transactions are scheduled to execute concurrently. Smartly relaxing the isolation properties of transactions may overcome these issues and attain considerable performance improvements. However, it is known that relaxing isolation restrictions may lead to runtime anomalies. In some situations, like database management systems, developers may choose that compromise, hence avoiding anomalies explicitly. Memory transactions protect the state of the program, therefore execution anomalies may have more severe consequences in the semantics of programs. So, the compromise between a relaxed isolation strategy and enforcing the necessary program correctness is harder to setup. The solution we devise is to statically analyse programs to detect the kind of anomalies that emerge under snapshot isolation. Our approach allows a compiler to either warn the developer about the possible snapshot isolation anomalies in a given program, or possibly inform automatic correctness strategies to ensure Serializability.

}, url = {http://inforum.org.pt/INForum2010/papers/ciencia-e-engenharia-de-software/Paper053.pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/paper.pdf}, author = {Ricardo J. Dias and Seco,, Jo{\~a}o and Jo{\~a}o M. Louren{\c c}o} } @conference {teixeira10_inforum, title = {A Static Approach for Detecting Concurrency Anomalies in Transactional Memory}, booktitle = {Proceedings of INForum Simp{\'o}sio de Inform{\'a}tica (InForum 2010)}, year = {2010}, note = {

n/a

}, publisher = {Universidade do Minho}, organization = {Universidade do Minho}, address = {Braga, Portugal}, abstract = {

Programs containing concurrency anomalies will most probably exhibit harmful erroneous and unpredictable behaviors. To ensure program correctness, the sources of those anomalies must be located and corrected. Concurrency anomalies in Transactional Memory (TM) programs should also be diagnosed and fixed. In this paper we propose a framework to deal with two different categories of concurrency anomalies in TM. First, we will address low-level TM anomalies, also called dataraces, which arise from executing programs in weak isolation. Secondly, we will address high-level TM anomalies, also called high-level dataraces, bringing the programmers attention to pairs of transactions that the programmer has misspecified, and should have been combined into a single transaction. Our framework was validated against a set of programs with well known anomalies and demonstrated high accuracy and effectiveness, thus contributing for improving the correctness of TM programs

}, url = {http://inforum.org.pt/INForum2010/papers/compiladores-e-linguagens-de-programacao/Paper125.pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/paper-lncs.pdf}, author = {Teixeira, Bruno and Jo{\~a}o M. Louren{\c c}o and Sousa, Diogo} } @proceedings {lpdsgv-eurosys-2009, title = {NGenVM: New Generation Execution Environments}, journal = {EuroSys}, year = {2009}, note = {

Poster presented at EuroSys{\textquoteright}2009

}, address = {Nuremberg, Germany}, abstract = {

This document describes a work-in-progress development of NGen-VM, a distributed infrastructure that manages execution environments with run-time and programming language support targeting applications developed in the Java programming language, deployed over clusters of many-core computers. For each running application or suite of related applications, a dedicated single-system image will be provided, regardless of the concurrent threads running on a single machine (on several cores) or scattered on different computers. Such system images rely on a single model for concurrency management (Transactional Shared Memory Model), in order fill the gap between the hardware infrastructure of clusters of many-core nodes and the application runtime that is independent from that hardware infrastructure. Interactions between threads in the same tasks will be supported by a Transactional Memory framework that provides the programming language with Atomic and Isolated code regions. Interactions between thread on different machines will also use the Transactional Memory model, but now resorting to a Distributed Shared Memory abstraction.

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/ngenvm-poster-completo.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Pregui{\c c}a, Nuno and Ricardo J. Dias and Silva, Jo{\~a}o Nuno and Garcia, Jo{\~a}o and Veiga, Lu{\'\i}s} } @conference {Lourenco:2009:UBT:1639622.1639625, title = {Understanding the Behavior of Transactional Memory Applications}, booktitle = {Proceedings of the 7th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging (PADTAD{\textquoteright}09)}, series = {{PADTAD}{\textquoteright}09}, year = {2009}, pages = {31{\textendash}39}, publisher = {ACM}, organization = {ACM}, address = {New York, NY, USA}, abstract = {

Transactional memory is a new trend in concurrency control that was boosted by the advent of multi-core processors and the near to come many-core processors. It promises the performance of finer grain with the simplicity of coarse grain threading. However, there is a clear absence of software development tools oriented to the transactional memory programming model, which is confirmed by the very small number of related scientific works published until now. This paper describes ongoing work. We propose a very low overhead monitoring framework, developed specifically for monitoring TM computations, that collects the transactional events into a single log file, sorted in a global order. This framework is then used by a visualization tool to display different types of charts from two categories: statistical charts and thread-time space diagrams. These last diagrams are interactive, allowing to identify conflicting transactions. We use the visualization tool to analyse the behavior of two different, but similar, testing applications, illustrating how it can be used to better understand the behavior of these transactional memory applications.

}, keywords = {concurrency, debugging, monitoring, profiling, software transactional memory, testing, visualization}, isbn = {9781-605-5865-5-7}, doi = {10.1145/1639622.1639625}, url = {http://doi.acm.org/10.1145/1639622.1639625}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/padtad2009.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Ricardo J. Dias and Lu{\'\i}s, Jo{\~a}o and Rebelo, Miguel and Pessanha, Vasco} } @conference {Dias:2009:UMD:1616772.1616813, title = {Unifying Memory and Database Transactions}, booktitle = {Proceedings of the 15th International Euro-Par Conference on Parallel Processing}, series = {{Euro-Par}{\textquoteright}09}, year = {2009}, note = {

n/a

}, pages = {349{\textendash}360}, publisher = {Springer-Verlag}, organization = {Springer-Verlag}, address = {Berlin, Heidelberg}, abstract = {

Software Transactional Memory is a concurrency control technique gaining increasing popularity, as it provides high-level concurrency control constructs and eases the development of highly multi-threaded applications. But this easiness comes at the expense of restricting the operations that can be executed within a memory transaction, and operations such as terminal and file I/O are either not allowed or incur in serious performance penalties. Database I/O is another example of operations that usually are not allowed within a memory transaction. This paper proposes to combine memory and database transactions in a single unified model, benefiting from the ACID properties of the database transactions and from the speed of main memory data processing. The new unified model covers, without differentiating, both memory and database operations. Thus, the users are allowed to freely intertwine memory and database accesses within the same transaction, knowing that the memory and database contents will always remain consistent and that the transaction will atomically abort or commit the operations in both memory and database. This approach allows to increase the granularity of the in-memory atomic actions and hence, simplifies the reasoning about them.

}, isbn = {978-3-642-03868-6}, doi = {10.1007/978-3-642-03869-3_35}, url = {http://dx.doi.org/10.1007/978-3-642-03869-3_35}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/europar2009-umadt.pdf}, author = {Ricardo J. Dias and Jo{\~a}o M. Louren{\c c}o} } @conference {Preguica:2008:BBD:1855556.1855565, title = {Byzantium: Byzantine-fault-tolerant database replication providing snapshot isolation}, booktitle = {Proceedings of the Fourth conference on Hot topics in system dependability}, series = {{HotDep}{\textquoteright}08}, year = {2008}, note = {

n/a

}, pages = {9{\textendash}9}, publisher = {USENIX Association}, organization = {USENIX Association}, address = {Berkeley, CA, USA}, abstract = {

Database systems are a key component behind many of today{\textquoteright}s computer systems. As a consequence, it is crucial that database systems provide correct and continuous service despite unpredictable circumstances, such as software bugs or attacks. This paper presents the design of Byzantium, a Byzantine fault-tolerant database replication middleware that provides snapshot isolation (SI) semantics. SI is very popular because it allows increased concurrency when compared to serializability, while providing similar behavior for typical workloads. Thus, Byzantium improves on existing proposals by allowing increased concurrency and not relying on any centralized component. Our middleware can be used with off-the-shelf database systems and it is built on top of an existing BFT library.

}, url = {http://portal.acm.org/citation.cfm?id=1855556.1855565}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/byzantium-hotdep.pdf}, author = {Pregui{\c c}a, Nuno and Rodrigues, Rodrigo and Honorato, Crist{\'o}v{\~a}o and Jo{\~a}o M. Louren{\c c}o} } @conference {CunhaLD:JETC:2008, title = {Consistent State Software Transactional Memory}, booktitle = {IV Jornadas de Engenharia de Electr{\'o}nica e Telecomunica{\c c}{\~o}es e de Computadores (JETC{\textquoteright}08)}, year = {2008}, note = {

n/a

}, pages = {251{\textendash}256}, publisher = {ISEL - Instituto Superior de Engenharia de Lisboa}, organization = {ISEL - Instituto Superior de Engenharia de Lisboa}, address = {Lisboa, Portugal}, abstract = {

Software transactional memory (STM) is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to memory (RAM) locations. In this paper we propose a new classification for the active states of a transaction; a new memory quiescing algorithm, to allow the safe transition of a memory block form transactional to non-transactional space; we compare word and object transactional grain units; and evaluate the cost of consistent state validation, arguing that this cost can be minimized by performing partial validation on problematic code regions.

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/jetc_2008.pdf}, author = {Cunha, Gon{\c c}alo and Louren{\c c}o, Jo{\~a}o and Ricardo J. Dias}, editor = {ISBN: 9789729580949} } @article {DBLP:journals/comsis/DiasLC08, title = {Developing libraries using software transactional memory}, journal = {Comput. Sci. Inf. Syst.}, volume = {5}, number = {2}, year = {2008}, note = {

n/a

}, pages = {103{\textendash}117}, abstract = {

Software transactional memory is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to main memory (RAM). This paper discusses how to support revertible operations, such as memory allocation and release, within software libraries that will be used in software memory transactional contexts. The proposal is based in the extension of the transaction life cycle state diagram with new states associated to the execution of user-defined handlers. The proposed approach is evaluated in terms of functionality and performance by way of a use case study and performance tests. Results demonstrate that the proposal and its current implementation are flexible, generic and efficient

}, keywords = {compensation actions, revertible operations, software transactional memory, transactions}, doi = {10.2298/CSIS0802103D}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/comsis_final.pdf}, author = {Ricardo J. Dias and Jo{\~a}o M. Louren{\c c}o and Cunha, Gon{\c c}alo} } @conference {DiasLC:CoRTA:2008, title = {Developing Libraries Using Software Transactional Memory}, booktitle = {CoRTA 2008: Proceedings of the Conference on Compilers, Related Technologies and Applications}, year = {2008}, note = {

n/a

}, publisher = {Instituto Polit{\'e}cnico de Bragan{\c c}a - ESTG}, organization = {Instituto Polit{\'e}cnico de Bragan{\c c}a - ESTG}, address = {Bragan{\c c}a, Portugal}, abstract = {

Software transactional memory (STM) is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to main memory (RAM) locations. This paper aims at discussing how to support apparently irreversible operations within a memory transaction.

}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/corta_2008.pdf}, author = {Ricardo J. Dias and Louren{\c c}o, Jo{\~a}o and Cunha, Gon{\c c}alo} } @conference {Dikaiakos:2008:TST:1429623.1429625, title = {Topic 1: Support Tools and Environments}, booktitle = {Euro-Par 2008 Parallel Processing}, series = {Lecture Notes in Computer Science}, volume = {5168}, year = {2008}, note = {n/a}, pages = {1{\textendash}2}, publisher = {Springer-Verlag}, organization = {Springer-Verlag}, address = {Berlin, Heidelberg}, abstract = {

The spread of systems that provide parallelism either {\guillemotleft}in-the-large{\guillemotright} (grid infrastructures, clusters) or {\guillemotleft}in-the-small{\guillemotright} (multi-core chips), creates new opportunities for exploiting parallelism in a wider spectrum of application domains. However, the increasing complexity of parallel and distributed platforms renders the programming, the use, and the management of these systems a costly endeavor that requires advanced expertise and skills. Therefore, there is an increasing need for powerful support tools and environments that will help end-users, application programmers, software engineers and system administrators to manage the increasing complexity of parallel and distributed platforms.

}, isbn = {978-3-540-85450-0}, issn = {0302-9743}, doi = {10.1007/978-3-540-85451-7_1}, url = {http://dx.doi.org/10.1007/978-3-540-85451-7_1}, author = {Dikaiakos, Marios and Rana, Omer and Ur, Shmuel and Jo{\~a}o M. Louren{\c c}o} } @conference {Lourenco:2007:TPS:1273647.1273655, title = {Testing patterns for software transactional memory engines}, booktitle = { Proceedings of the 5th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging (PADTAD{\textquoteright}07)}, series = {{PADTAD}{\textquoteright}07}, year = {2007}, pages = {36{\textendash}42}, publisher = {ACM}, organization = {ACM}, address = {New York, NY, USA}, abstract = {

The emergence of multi-core processors is promoting the use of concurrency and multithreading. To raise the abstraction level of synchronization constructs is fundamental to ease the development of concurrent software, and Software Transactional Memory (STM) is a good approach towards such goal. However, execution environment issues such as the processor instruction set, caching policy, and memory model, may have strong influence upon the reliability of STM engines. This paper addresses the testing of STM engines aiming at improving their reliability and independence from execution environment. From our experience with porting and extending a specific STM engine, we report on some of the bugs found and synthesize some testing patterns that proved to be useful at testing STM engines.

}, keywords = {concurrency, debugging, software transactional memory, testing, testing patterns}, isbn = {9781-595-9374-8-3}, doi = {10.1145/1273647.1273655}, url = {http://dx.doi.org/10.1145/1273647.1273655}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/padtad21s.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Cunha, Gon{\c c}alo} } @proceedings {Cunha:2005:1067445, title = {Proceedings of the 10th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education (ITiCSE{\textquoteright}05)}, year = {2005}, note = {

457054

}, publisher = {ACM}, address = {New York, NY, USA}, abstract = {

n/a

}, isbn = {1-59593-024-8}, url = {http://dl.acm.org/citation.cfm?id=1067445}, author = {Cunha, Jos{\'e} C. and Fleischman, William and Jo{\~a}o M. Louren{\c c}o and Proulx, Viera K.}, editor = {Cunha, Jos{\'e} C. and Fleischman, William and Louren{\c c}o, Jo{\~a}o and Proulx, Viera K.} } @mastersthesis {jml-phd, title = {A Debugging Engine for Parallel and Distributed Programs}, year = {2004}, note = {

n/a

}, school = {Faculdade de Ci{\^e}ncias e Tecnologia}, type = {PhD thesis}, abstract = {

In the last decade a considerable amount of research work has focused on distributed debugging, one of the crucial fields in the parallel software development cycle. The productivity of the software development process strongly depends on the adequate definition of what debugging tools should be provided, and what debugging methodologies and functionalities should these tools support. The work described in this dissertation was initiated in 1995, in the context of two research projects, the SEPP (Software Engineering for Parallel Processing) and HPCTI (High-Performance Computing Tools for Industry), both sponsored by the European Union in the Copernicus program, which aimed at the design and implementation of an integrated parallel software development environment. In the context of these projects, two independent toolsets have been developed, the GRADE and EDPEPPS parallel software development environments. Our contribution to these projects was in the debugging support. We have designed a debugging engine and developed a prototype, which was integrated the both toolsets (it was the only tool developed in the context of the SEPP and HPCTI projects which achieved such a result). Even after the closing of those research projects, further research work on distributed debugger has been carried on, which conducted to the re-design and re-implementation of the debugging engine. This dissertation describes the debugging engine according to its most up-to-date design and implementation stages. It also reposts some of the experimental work made with both the initial and the current implementations, and how it contributed to validate the design and implementations of the debugging engine.

}, url = {http://hdl.handle.net/10362/2314}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/fiddle-thesis.pdf}, author = {Jo{\~a}o M. Louren{\c c}o}, editor = {Cunha, Jos{\'e} C.} } @article {DBLP:journals/corr/cs-DC-0309049, title = {Control and Debugging of Distributed Programs Using Fiddle}, journal = {CoRR}, volume = {cs.DC/0309049}, year = {2003}, note = {

n/a

}, pages = {143{\textendash}157}, abstract = {

n/a

}, url = {http://arxiv.org/abs/cs.DC/0309049}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/aadebug.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Cunha, Jos{\'e} C. and Vitor Moreira} } @inbook {Duarte:2004:SOD:1024677.1024681, title = {Supporting on-line distributed monitoring and debugging}, booktitle = {On-Line Monitoring Systems and Computer Tool Interoperability}, year = {2003}, note = {

n/a

}, pages = {43{\textendash}59}, publisher = {Nova Science Publishers, Inc.}, organization = {Nova Science Publishers, Inc.}, address = {Commack, NY, USA}, abstract = {

Monitoring systems have traditionally been developed with rigid objectives and functionalities, and tied to specific languages, libraries and run-time environments. There is a need for more flexible monitoring systems which can be easily adapted to distinct requirements. On-line monitoring has been considered as increasingly important for observation and control of a distributed application. In this paper we discuss monitoring interfaces and architectures which support more extensible monitoring and control services. We describe our work on the development of a distributed monitoring infrastructure, and illustrate how it eases the implementation of a complex distributed debugging architecture. We also discuss several issues concerning support for tool interoperability and illustrate how the cooperation among multiple concurrent tools can ease the task of distributed debugging.

}, keywords = {distributed debugging, environments, on-line monitoring, software engineering, tool interoperability}, isbn = {1-59033-888-X}, url = {http://portal.acm.org/citation.cfm?id=1024677.1024681}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/pdcp_0.pdf}, author = {Duarte, Vitor and Jo{\~a}o M. Louren{\c c}o and Cunha, Jos{\'e} C.} } @inbook {Cunha:2001:DDD:379741.379773, title = {The DDBG distributed debugger}, booktitle = {Parallel Program Development for Cluster Computing}, year = {2001}, note = {

n/a

}, pages = {279{\textendash}290}, publisher = {Nova Science Publishers, Inc.}, organization = {Nova Science Publishers, Inc.}, address = {Commack, NY, USA}, abstract = {

n/a

}, isbn = {1-56072-865-5}, url = {http://portal.acm.org/citation.cfm?id=379741.379773}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/cap13.pdf}, author = {Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o and Duarte, Vitor} } @inbook {Cunha:2001:DPD:379741.379761, title = {Debugging of parallel and distributed programs}, booktitle = {Parallel Program Development for Cluster Computing}, year = {2001}, note = {

n/a

}, pages = {97{\textendash}129}, publisher = {Nova Science Publishers, Inc.}, organization = {Nova Science Publishers, Inc.}, address = {Commack, NY, USA}, abstract = {

n/a

}, isbn = {1-56072-865-5}, url = {http://portal.acm.org/citation.cfm?id=379741.379761}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/cap03.pdf}, author = {Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o and Duarte, Vitor} } @conference {Lourenco:2001:FFD:645456.654826, title = {Fiddle: A Flexible Distributed Debugging Architecture}, booktitle = {Proceedings of the International Conference on Computational Science-Part II}, series = {{ICCS}{\textquoteright}01}, year = {2001}, note = {

n/a

}, pages = {821{\textendash}830}, publisher = {Springer-Verlag}, organization = {Springer-Verlag}, address = {London, UK}, abstract = {

In the recent past, multiple techniques and tools have been proposed and contributed to improve the distributed debugging functionalities, in several distinct aspects, such as handling the non-determinism, allowing cyclic interactive debugging of parallel programs, and providing more user-friendly interfaces. However, most of these tools are tied to a specific programming language and provide rigid graphical user interfaces. So they cannot easily adapt to support distinct abstraction levels or user interfaces. They also don{\textquoteright}t provide adequate support for cooperation with other tools in a software engineering environment. In this paper we discuss several dimensions which may contribute to develop more flexible distributed debuggers. We describe Fiddle, a distributed debugging tool which aims at overcoming some of the above limitations.

}, isbn = {3-540-42233-1}, issn = {0302-9743}, url = {http://portal.acm.org/citation.cfm?id=645456.654826}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/lourenco001.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Cunha, Jos{\'e} C.} } @article {pdcp:2001, title = {Supporting On-line Distributed Monitoring and Debugging}, journal = {Parallel and Distributed Computing Practices}, volume = {4}, number = {3}, year = {2001}, note = {

n/a

}, pages = {43{\textendash}59}, abstract = {

Monitoring systems have traditionally been developed with rigid objectives and functionalities, and tied to specific languages, libraries and run-time environments. There is a need for more flexible monitoring systems which can be easily adapted to distinct requirements. On-line monitoring has been considered as increasingly important for observation and control of a distributed application. In this paper we discuss monitoring interfaces and architectures which support more extensible monitoring and control services. We describe our work on the development of a distributed monitoring infrastructure, and illustrate how it eases the implementation of a complex distributed debugging architecture. We also discuss several issues concerning support for tool interoperability and illustrate how the cooperation among multiple concurrent tools can ease the task of distributed debugging.

}, issn = {1097-2803}, url = {http://www.scpe.org/index.php/scpe/article/view/247}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/pdcp.pdf}, author = {Duarte Vitor, Louren{\c c}o Jo{\~a}o M., Cunha Jos{\'e} C.} } @article {Cunha:1999:ETI:315247.315257, title = {An experiment in tool integration: the {DDBG} parallel and distributed debugger}, journal = {J. Syst. Archit.}, volume = {45}, year = {1999}, note = {

n/a

}, month = {may}, pages = {897{\textendash}907}, publisher = {Elsevier North-Holland, Inc.}, address = {New York, NY, USA}, abstract = {

Most known teaching experiences focus on parallel computing courses only, but some teaching experiences on distributed computing courses have also been reported. In this paper we describe a course on Parallel and Distributed Processing that is taught at undergraduate level in the Computer Science degree of our University.This course presents an integrated approach concerning concurrency, parallelism, and distribution issues. It{\textquoteright}s a breadth-first course addressing a wide spectrum of abstractions: the theoretical component focus on the fundamental abstractions to model concurrent systems, including process cooperation schemes, concurrent programming models, data and control distribution, concurrency control and recovery in transactional systems, and parallel processing models; the practical component illustrates the design and implementation issues involved in selected topics such as a data and control distribution problem, a distributed transaction-based support system and a parallel algorithm.We also discuss how this approach has been contributing to prepare the student to further actions regarding research and development of concurrent, distributed, or parallel systems.

}, keywords = {debugging, monitoring, parallel programming environments}, issn = {1383-7621}, doi = {10.1016/S1383-7621(98)00024-1}, url = {http://dx.doi.org/10.1016/S1383-7621(98)00024-1}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/jsa99.pdf}, author = {Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o and Ant{\~a}o, Tiago} } @conference {DBLP:conf/pdpta/CunhaMDLG99, title = {An Experience in Building a Parallel and Distributed Problem-Solving Environment}, booktitle = {Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA{\textquoteright}99)}, year = {1999}, note = {

n/a

}, pages = {1804{\textendash}1809}, publisher = {CSREA Press}, organization = {CSREA Press}, abstract = {

We describe our experimentation with the design and implementation of specific environments, consisting of heterogeneous computational, visualization, and control components. We illustrate the approach with the design of a problem–solving environment supporting the execution of genetic algorithms. We describe a prototype supporting parallel execution, visualization, and steering. A life cycle for the development of applications based on genetic algorithms is proposed.

}, isbn = {1-892512-15-7}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/pdpta99.pdf}, author = {Cunha, Jos{\'e} C. and Medeiros, Pedro D. and Duarte, Vitor and Louren{\c c}o, Jo{\~a}o and Gomes, Cecilia} } @conference {Cunha:1998:DPT:645562.659835, title = {The DOTPAR Project: Towards a Framework Supporting Domain Oriented Tools for Parallel and Distributed Processing}, booktitle = {Proceedings of the International Conference and Exhibition on High-Performance Computing and Networking (HPCN{\textquoteright}98)}, series = {HPCN Europe 1998}, year = {1998}, note = {

n/a

}, pages = {952{\textendash}954}, publisher = {Springer-Verlag}, organization = {Springer-Verlag}, address = {London, UK}, abstract = {

We discuss the problem of building domain oriented environments by a composition of heterogeneous application components and tools. We describe several individual tools that support such environments, namely a distributed monitoring and control tool (DAMS), a process-based distributed debugger (PDBG) and a heterogeneous interconnection model (PHIS). We discuss our experience with the development of a Problem Oriented Environment in the domain of genetic algorithms, obtained by a composition of heterogeneous tools and application components.

}, isbn = {3-540-64443-1}, url = {http://portal.acm.org/citation.cfm?id=645562.659835}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/dotpar98.pdf}, author = {Cunha, Jos{\'e} C. and Medeiros, Pedro D. and Jo{\~a}o M. Louren{\c c}o and Duarte, V{\'\i}tor and Vieira, Jo{\~a}o and Mosc{\~a}o, Bruno and Pereira, Daniel and Vaz, Rui} } @conference {Cunha:1998:FSP:645562.659536, title = {A Framework to Support Parallel and Distributed Debugging}, booktitle = {Proceedings of the International Conference and Exhibition on High-Performance Computing and Networking (HPCN{\textquoteright}98)}, series = {HPCN Europe 1998}, year = {1998}, note = {

n/a

}, pages = {708{\textendash}717}, publisher = {Springer-Verlag}, organization = {Springer-Verlag}, address = {London, UK}, abstract = {

We discuss debugging prototypes that can easily support new functionalities, depending on the requirements of high-level computational models, and allowing a coherent integration with other tools in a software engineering environment. Concerning the first aspect, we propose a framework that identifies two distinct levels of functionalities that should be supported by a parallel and distributed debugger using: a process and thread-level, and a coordination level concerning sets of processes or threads. An incremental approach is used to effectively develop prototypes that support both functionalities. Concerning the second aspect, we discuss how the interfacing with other tools has influenced the design of a process-level debugging interface (PDBG) and a distributed monitoring and control layer called (DAMS).

}, isbn = {3-540-64443-1}, url = {http://portal.acm.org/citation.cfm?id=645562.659536}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/hpcn98.pdf}, author = {Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o and Vieira, Jo{\~a}o and Mosc{\~a}o, Bruno and Pereira, Daniel} } @article {Cunha:1998:ICP:274790.274300, title = {An Integrated Course on Parallel and Distributed Processing}, journal = {SIGCSE Bull.}, volume = {30}, year = {1998}, pages = {217{\textendash}221}, publisher = {ACM}, address = {New York, NY, USA}, abstract = {

Most known teaching experiences focus on parallel computing courses only, but some teaching experiences on distributed computing courses have also been reported. In this paper we describe a course on Parallel and Distributed Processing that is taught at undergraduate level in the Computer Science degree of our University.This course presents an integrated approach concerning concurrency, parallelism, and distribution issues. It{\textquoteright}s a breadth-first course addressing a wide spectrum of abstractions: the theoretical component focus on the fundamental abstractions to model concurrent systems, including process cooperation schemes, concurrent programming models, data and control distribution, concurrency control and recovery in transactional systems, and parallel processing models; the practical component illustrates the design and implementation issues involved in selected topics such as a data and control distribution problem, a distributed transaction-based support system and a parallel algorithm.We also discuss how this approach has been contributing to prepare the student to further actions regarding research and development of concurrent, distributed, or parallel systems.

}, issn = {0097-8418}, doi = {10.1145/274790.274300}, url = {http://doi.acm.org/10.1145/274790.274300}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/sigcse98.pdf}, author = {Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o} } @conference {Lourenco:1998:PPD:281035.281056, title = {The PDBG Process-Level Debugger for Parallel and Distributed Programs}, booktitle = {Proceedings of the SIGMETRICS symposium on Parallel and Distributed Tools}, series = {{SPDT}{\textquoteright}98}, year = {1998}, pages = {154}, publisher = {ACM}, organization = {ACM}, address = {New York, NY, USA}, abstract = {

In this paper we discuss several issues concerning the design and implementation of a debugger for parallel and distributed applications. This debugger uses a client-server approach to isolate the debugging user-interface from the debugging services, by way of a two-level structured approach: the component-level to observe and act upon individual processes; and the coordination-level to observe the interprocess relations and act upon them.

}, isbn = {1-58113-001-5}, doi = {10.1145/281035.281056}, url = {http://doi.acm.org/10.1145/281035.281056}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/spdt-asbt98.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Cunha, Jos{\'e} C.} } @conference {Lourenco.Cunha-105ip-98, title = {Replaying Distributed Applications with RPVM}, booktitle = {Proceeding of the 2nd Austrian-Hungarian Workshop on Distributed and Parallel Systems (DAPSYS{\textquoteright}98)}, year = {1998}, note = {

n/a

}, publisher = {University of Vienna}, organization = {University of Vienna}, abstract = {

Parallel debugging is complex and difficult. Complex because the programmer has to deal with multiple program flows and process interactions, and difficult due to the very limited choice on effective and easy-to-use debugging tools for parallel programming. Simple and necessary features for parallel debugging are absent even from commercial debuggers, such as a record-replay feature, that allows to re-execute multiple times a parallel application assuring that during each re-execution the internal race conditions are solved in the same way they were in the first time. Some work has been done on record-replay techniques for parallel and distributed applications, but just a few have been applied to specific systems (such as PVM or MPI), and even less have produced working prototypes. In this paper we describe a method designed to work with the PVM system and how it was implemented to provide a working prototype.

}, url = {http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.12.5057\&rep=rep1\&type=pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/dapsys98.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Cunha, Jos{\'e} C.} } @conference {Lourenco.Cunha-109ip-98, title = {A Thread-Level Distributed Debugger}, booktitle = {Proceedings of the 3rd International Conference on Vector and Parallel Processing (VecPar{\textquoteright}98)}, year = {1998}, note = {

n/a

}, pages = {359{\textendash}366}, publisher = {Universidade do Porto}, organization = {Universidade do Porto}, address = {Porto, Portugal}, abstract = {

In order to address the diversity of existing parallel programming models, it is important to provide development environments that can be incrementally extended with new services. Concerning the debugging of process based models, we have previously designed and implemented a basic interface that can be accessed by other tools as well as by debugging modules associated with high-level programming languages.

}, url = {http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.12.7983\&rep=rep1\&type=pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/vecpar98.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Cunha, Jos{\'e} C.} } @conference {seihpc:1998, title = {Tool Integration Issues for Parallel and Distributed Debugging}, booktitle = {Proceedings of the 3rd SEIHPC Workshop}, year = {1998}, note = {

n/a

}, publisher = {University of Westminster}, organization = {University of Westminster}, address = {Braga, Portugal}, abstract = {

This paper describes our experience with the design and implementation of a distributed debugger for C/PVM programs within the scope of the SEPP and HPCTI Copernicus projects. These projects aimed at the development of an integrated parallel software engineering environment based on a high-level graphical parallel programming model (GRAPNEL) and a set of associated tools supporting graphical edition, compilation, simulated and real parallel execution, testing, debugging, performance monitoring, mapping, and load balancing. We discuss how the development of the debugging tool was strongly influenced by the requirements posed by other tools in the environment, namely support for high-level graphical debugging of GRAPNEL programs, and support for the integration of static and dynamic analysis tools. We describe the functionalities of the DDBG debugger and its internal architecture, and discuss its integration with two separate tools in the SEPP/HPCTI environment: the GRED graphical editor for GRAPNEL programs, and the STEPS testing tool for C/PVM programs.

}, url = {http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.13.2752\&rep=rep1\&type=pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/seihpc98.pdf}, author = {Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o and Duarte, Vitor} } @article {DBLP:journals/cai/CunhaLD98, title = {Using DDBG to Support Testing and High-level Debugging Interfaces}, journal = {Computers and Artificial Intelligence}, volume = {17}, number = {5}, year = {1998}, note = {

n/a

}, abstract = {

This paper describes our experience with the design and implementation of a distributed debugger for C/PVM programs within the scope of the SEPP and HPCTI Copernicus projects. These projects aimed at the development of an integrated parallel software engineering environment based on a high-level graphical parallel programming model (GRAPNEL) and a set of associated tools supporting graphical edition, compilation, simulated and real parallel execution, testing, debugging, performance monitoring, mapping, and load balancing. We discuss how the development of the debugging tool was strongly influenced by the requirements posed by other tools in the environment, namely support for high-level graphical debugging of GRAPNEL programs, and support for the integration of static and dynamic analysis tools. We describe the functionalities of the DDBG debugger and its internal architecture, and discuss its integration with two separate tools in the SEPP/HPCTI environment: the GRED graphical editor for GRAPNEL programs, and the STEPS testing tool for C/PVM programs.

}, url = {http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.12.4150\&rep=rep1\&type=pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/caij98.pdf}, author = {Cunha, Jos{\'e} C. and Louren{\c c}o, Jo{\~a}o and Duarte, Vitor} } @article {Kacsuk:1997:GDD:251146.251151, title = {A graphical development and debugging environment for parallel programs}, journal = {Parallel Comput.}, volume = {22}, year = {1997}, note = {

n/a

}, pages = {1747{\textendash}1770}, publisher = {Elsevier Science Publishers B. V.}, address = {Amsterdam, The Netherlands, The Netherlands}, abstract = {

To provide high-level graphical support for PVM (Parallel Virtual Machine) based program development, a complex programming environment (GRADE) is being developed. GRADE currently provides tools to construct, execute, debug, monitor and visualise message-passing parallel programs. It offers high-level graphical programming abstraction mechanism to construct parallel applications by introducing a new graphical language called GRAPNEL. GRADE also provides the programmer with the same graphical user interface during the program design and debugging stages. A distributed debugging engine (DDBG) assists the user in debugging GRAPNEL programs on distributed memory computer architectures. Tape/PVM and PROVE support the performance monitoring and visualization of parallel programs developed in the GRADE environment.

}, keywords = {debugging, graphical programming language, parallel processing, software tools}, issn = {0167-8191}, doi = {10.1016/S0167-8191(96)00075-0}, url = {http://portal.acm.org/citation.cfm?id=251146.251151}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/par-comp97.pdf}, author = {Kacsuk, P{\'e}ter and Cunha, Jos{\'e} C. and D{\'o}zsa, G{\'a}bor and Jo{\~a}o M. Louren{\c c}o and Fadgyas, Tibor and Ant{\~a}o, Tiago} } @article {10.1109/EURMIC.1997.617289, title = {An integrated testing and debugging environment for parallel and distributed programs}, journal = {EUROMICRO Conference}, year = {1997}, pages = {291}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, abstract = {

To achieve a certain degree of confidence that a given program follows its specification, a testing phase must be included in the program development process, and also a complementary debugging phase to help locating the program{\textquoteright}s bugs. This paper presents an environment which results of the composition and integration of two basic tools: STEPS (Structural TEsting of Parallel Software), which is a testing tool, and DDBG (Distributed DeBuGger), which is a debugging tool. The two tools are presented individually as stand-alone tools, and we describe how they were combined through the use of another intermediate tool: DEIPA (Deterministic re-Execution and Interactive Program Analysis). We claim that the result achieved is a very effective testing and debugging environment.

}, issn = {1089-6503}, doi = {10.1109/EURMIC.1997.617289}, url = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.617289}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/euromicro97.pdf}, author = {Jo{\~a}o M. Louren{\c c}o and Cunha, Jos{\'e} C. and Krawczyk, H. and Kuzora, P. and Neyman, M. and Wiszniewski, B.} } @conference {Cun.Lou.Ant-128ip-96, title = {A Distributed Debugging Tool for a Parallel Software Engineering Environment}, booktitle = {Proceedings of the 1st European Parallel Tools Meeting (EPTM{\textquoteright}96)}, year = {1996}, month = {October}, publisher = {ONERA (French National Establishment for Aerospace Research)}, organization = {ONERA (French National Establishment for Aerospace Research)}, address = {Paris, France}, abstract = {

We discuss issues in the design and implementation of a flexible debugging tool and its integration into a parallel software engineering environment.

}, url = {http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.63.9674\&rep=rep1\&type=pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/eptm96.pdf}, author = {Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o and Ant{\~a}o, Tiago} } @conference {Cun.Lou.Ant-131ip-96, title = {A Debugging Engine for a Parallel and Distributed Environment}, booktitle = {Proceedings of the 1st Austrian-Hungarian Workshop on Distributed and Parallel Systems (DAPSYS{\textquoteright}96)}, year = {1996}, note = {

n/a

}, pages = {111{\textendash}118}, publisher = {Hungarian Academy of Sciences, KFKI}, organization = {Hungarian Academy of Sciences, KFKI}, address = {Wien, Austria}, abstract = {

This paper describes a debugging interface that has been developed for a parallel software engineering environment and that was developed on top of the PVM environment in the scope of the SEPP and HPCTI projects of the COPERNICUS Program. The main goal of this interface is to provide the basic debugging functionalities that are required by some components of that environment. We give special attention to the requirements posed by high-level tools of the environment, and to the need of providing a flexible debugging support layer that can be suitably adapted and extended. We present the system logical architecture and the interface specification of the debugging engine. We discuss its interfacing with other components of the environment, namely a graphical editor for the GRAPNEL visual parallel programming language, and a testing tool. We finally describe current work on the improvement of the debugging engine. Keywords: Debugging, monitoring, parallel processing, software tools.

}, url = {http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.22.9063\&rep=rep1\&type=pdf}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/dapsys96.pdf}, author = {Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o and Ant{\~a}o, Tiago} } @article {Kwiatkowski:1996:TPP:1013718.237633, title = {Teaching parallel processing: development of curriculum and software tools}, journal = {SIGCUE Outlook}, volume = {24}, year = {1996}, pages = {159{\textendash}161}, publisher = {ACM}, address = {New York, NY, USA}, abstract = {

This paper presents an approach to education in Parallel and Distributed Processing undertaken in the Technical University of Gdansk and Technical University of Wroclaw. The paper gives a detailed structure of the project entitled "Teaching Parallel Processing: Development of Curriculum and Software Tools" which was started in 1994 and will be finish in 1997. Two universities from Poland: Technical University of Gdansk and Technical University of Wroclaw and two universities from EC countries: University Aut{\`o}noma of Barcelona from Spain and University Nova of Lisbon from Portugal participate in the presented project. The main aim of the project is to develop existing curricula of Computer Science specialisation and to establish specialisation concerned with parallel and distributed processing at Polish universities.

}, issn = {0163-5735}, doi = {10.1145/1013718.237633}, url = {http://doi.acm.org/10.1145/1013718.237633}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/sigcse96.pdf}, author = {Kwiatkowski, Jan and Andruszkiewicz, Marek and Luque, Emilio and Margalef, Tomas and Cunha, Jos{\'e} C. and Jo{\~a}o M. Louren{\c c}o and Krawczyk, Henryk and Szejko, Stanislaw} } @mastersthesis {jml-msc, title = {Mecanismos de Suporte {\`a} Execu{\c c}{\~a}o Concorrente de Programas em L{\'o}gica}, year = {1994}, school = {Faculdade de Ci{\^e}ncias e Tecnologia, Universidade Nova de Lisboa}, type = {MSc thesis}, abstract = {

A evolu{\c c}{\~a}o do hardware dos computadores para arquitecturas paralelas, incentivou a concep{\c c}{\~a}o de novos modelos de programa{\c c}{\~a}o e o desenvolvimento dos sistemas de suporte {\`a} execu{\c c}{\~a}o correspondentes, de forma a conseguir uma melhor explora{\c c}{\~a}o do paralelismo. A linguagem de programa{\c c}{\~a}o Prolog, pelas suas caracter{\'\i}sticas declarativas e operacionais, tem vindo a ser objecto de estudo nesta {\'a}rea, atrav{\'e}s de adapta{\c c}{\~o}es da linguagem e/ou da sua m{\'a}quina de infer{\^e}ncia. Este trabalho incide sobre os aspectos de concep{\c c}{\~a}o e implementa{\c c}{\~a}o de um modelo de um sistema de suporte {\`a} execu{\c c}{\~a}o de programas em Prolog, em arquitecturas de m{\'u}ltiplos processadores, com unidades de mem{\'o}ria fisicamente distribu{\'\i}das. O modelo prop{\~o}e extens{\~o}es a um executor de Prolog convencional, de forma a disponibilizar funcionalidades que permitam o controlo do paralelismo e da distribui{\c c}{\~a}o. Estas funcionalidades podem ser utilizadas para a implementa{\c c}{\~a}o de modelos de linguagens l{\'o}gicas concorrentes de mais alto n{\'\i}vel, ou ent{\~a}o serem utilizadas directamente para a programa{\c c}{\~a}o de sistemas distribu{\'\i}dos, em que m{\'u}ltiplos executores Prolog cooperam na resolu{\c c}{\~a}o de um golo, comunicando com base em mensagens. Para avaliar a funcionalidade do modelo proposto, concebeu-se e implementou-se um sistema de distribui{\c c}{\~a}o de golos Prolog, que permite recorrer a diversas estrat{\'e}gias para composi{\c c}{\~a}o sequencial e paralela de golos, escondendo os aspectos de gest{\~a}o expl{\'\i}cita dos recursos efectivos. A disserta{\c c}{\~a}o inclui uma discuss{\~a}o dos aspectos mais relevantes da realiza{\c c}{\~a}o do prot{\'o}tipo do modelo proposto sobre uma arquitectura baseada em Transputers.

}, url = {http://hdl.handle.net/10362/2313}, attachments = {https://docentes.fct.unl.pt/sites/default/files/joao-lourenco/files/msc-thesis94.pdf}, author = {Jo{\~a}o M. Louren{\c c}o}, editor = {Cunha, Jos{\'e} C.} }