FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model
- Citation:
- Mudrov, M., A. Zyuzev, K. Nesterov, and S. Valtchev, "FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model", Conference Proceedings - 2017 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017, United States, Institute of Electrical and Electronics Engineers Inc., 7, 2017.
Date Presented:
7Abstract:
The Hardware-in-the-Loop (HiL) systems become nowadays popular. In the same time, the Field Programmable Gate Arrays (FPGAs) allow for creating the HiL with time step 1 μs or less. The FPGA usually executes the numerical operations on Fixed Point variables. That is why during the FPGA-based HiL creation process it is important to select a proper number of bits for the modeled variables. A mathematical model based on the induction motor is selected as a basis for comparative tests between the floating point model and the fixed point model. In consequence, recommendations for the Bit Capacity (the length of the digital word) selection are given, based on the obtained results.
Notes:
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