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Book Chapter
Cunha, J. C., J. M. Lourenço, and V. Duarte, "The DDBG distributed debugger", Parallel Program Development for Cluster Computing, Commack, NY, USA, Nova Science Publishers, Inc., pp. 279–290, 2001. Abstractcap13.pdf


Cunha, J. C., J. M. Lourenço, and V. Duarte, "Debugging of parallel and distributed programs", Parallel Program Development for Cluster Computing, Commack, NY, USA, Nova Science Publishers, Inc., pp. 97–129, 2001. Abstractcap03.pdf


Dias, R. J., T. M. Vale, and J. M. Lourenço, "Framework Support for the Efficient Implementation of Multi-version Algorithms", Transactional Memory. Foundations, Algorithms, Tools, and Applications, vol. 8913: Springer International Publishing, pp. 166–191, 2015. Abstracttransactional_memory-dias_vale_lourenco.pdf

Software Transactional Memory algorithms associate metadata with the memory locations accessed during a transactions lifetime. This metadata may be stored in an external table and accessed by way of a function that maps the address of each memory location with the table entry that keeps its metadata (this is the out-place or external scheme); or alternatively may be stored adjacent to the associated memory cell by wrapping them together (the in-place scheme). In transactional memory multi-version algorithms, several versions of the same memory location may exist. The efficient implementation of these algorithms requires a one-to-one correspondence between each memory location and its list of past versions, which is stored as metadata. In this chapter we address the matter of the efficient implementation of multi-version algorithms in Java by proposing and evaluating a novel in-place metadata scheme for the Deuce framework. This new scheme is based in Java Bytecode transformation techniques and its use requires no changes to the application code. Experimentation indicates that multi-versioning STM algorithms implemented using our new in-place scheme are in average 6 × faster than when implemented with the out-place scheme.

Soares, J., J. M. Lourenço, and N. Preguiça, "MacroDB: Scaling Database Engines on Multicores", Euro-Par 2013 Parallel Processing, vol. 8097: Springer Berlin Heidelberg, pp. 607-619, 2013. Abstracteuropar2013-soares.pdf


Fiedor, J., Z. Letko, J. Lourenço, and T. Vojnar, "On Monitoring C/C++ Transactional Memory Programs", Mathematical and Engineering Methods in Computer Science, vol. 8934: Springer International Publishing, pp. 73–87, 2014. Abstractmemics14-monitoring-tm.pdf

Transactional memory (TM) is an increasingly popular technique for synchronising threads in multi-threaded programs. To address both correctness and performance-related issues of TM programs, one needs to monitor and analyse their execution. However, monitoring concurrent programs (including TM programs) may have a non-negligible impact on their behaviour, which may hamper the objectives of the intended analysis. In this paper, we propose several approaches for monitoring TM programs and study their impact on the behaviour of the monitored programs. The considered approaches range from specialised lightweight monitoring to generic heavyweight monitoring. The implemented monitoring tools are publicly available to the scientific community, and the implementation techniques used for lightweight monitoring of TM programs may be used as an inspiration for developing other specialised lightweight monitors.

Vale, T. M., R. J. Dias, and J. M. Lourenço, "On the Relevance of Total-Order Broadcast Implementations in Replicated Software Transactional Memories", Multicore Software Engineering, Performance, and Tools, vol. 8063: Springer Berlin Heidelberg, pp. 49-60, 2013. Abstractmusepat13-vale.pdf


Paulino, H., J. A. Martins, J. M. Lourenço, and N. Duro, "SmART: An Application Reconfiguration Framework", Complex Systems Design & Management: Springer Berlin Heidelberg, pp. 73–84, 2010. Abstractcsdm.pdf

SmART (Smart Application Reconfiguration Tool) is a framework for the automatic configuration of systems and applications. The tool implements an application configuration workflow that resorts to the similarities between configuration files (i.e., patterns such as parameters, comments and blocks) to allow a syntax independent manipulation and transformation of system and application configuration files.Without compromising its generality, SmART targets virtualized IT infrastructures, configuring virtual appliances and its applications. SmART reduces the time required to (re)configure a set of applications by automating time-consuming steps of the process, independently of the nature of the application to be configured. Industrial experimentation and utilization of SmART show that the framework is able to correctly transform a large amount of configuration files into a generic syntax and back to their original syntax. They also show that the elapsed time in that process is adequate to what would be expected of an interactive tool. SmART is currently being integrated into the VIRTU bundle, whose trial version is available for download from the projects web page.

Hollander, Y., A. Hu, J. M. Lourenço, and R. Morad, "Special Session on Debugging", Hardware and Software: Verification and Testing, vol. 6504: Springer Berlin / Heidelberg, pp. 24–28, 2011. Abstracthvc2010-secial_session_on_debugging.pdf

In software, hardware, and embedded system domains, debugging is the process of locating and correcting faults in a system. Depending on the context, the various characteristics of debugging induce different challenges and solutions. Post-silicon hardware debugging, for example, needs to address issues such as limited visibility and controllability, while debugging software entails other issues, such as the handling of distributed or non-deterministic computation. The challenges that accompany such issues are the focus of many current research efforts. Solutions for debugging range from interactive tools to highly analytic techniques. We have seen great advances in debugging technologies in recent years, but bugs continue to occur, and debugging still encompasses significant portions of the life-cycles of many systems. The session covered state-of-the-art approaches as well as promising new research directions in both the hardware and software domains.

Duarte, V., J. M. Lourenço, and J. C. Cunha, "Supporting on-line distributed monitoring and debugging", On-Line Monitoring Systems and Computer Tool Interoperability, Commack, NY, USA, Nova Science Publishers, Inc., pp. 43–59, 2003. Abstractpdcp.pdf

Monitoring systems have traditionally been developed with rigid objectives and functionalities, and tied to specific languages, libraries and run-time environments. There is a need for more flexible monitoring systems which can be easily adapted to distinct requirements. On-line monitoring has been considered as increasingly important for observation and control of a distributed application. In this paper we discuss monitoring interfaces and architectures which support more extensible monitoring and control services. We describe our work on the development of a distributed monitoring infrastructure, and illustrate how it eases the implementation of a complex distributed debugging architecture. We also discuss several issues concerning support for tool interoperability and illustrate how the cooperation among multiple concurrent tools can ease the task of distributed debugging.

Lourenço, J. M., "Understanding Transactional Memory (Extended Abstract)", Hardware and Software: Verification and Testing, vol. 6504: Springer Berlin / Heidelberg, pp. 1–2, 2011. Abstracthvc2010-understanding_transactional_memory.pdf

Transactional Memory [3] (TM) is a new paradigm for concurrency control that brings the concept of transactions, widely known from the Databases community, into the management of data located in main memory. TM delivers a powerful semantics for constraining concurrency and provides the means for the extensive use of the available parallel hardware. TM uses abstractions that promise to ease the development of scalable parallel applications by achieving performances close to fine-grained locking while maintaining the simplicity of coarse-grained locking.

Conference Paper
Oliveira, L. P., and J. M. Lourenço, "Aceleração de Computações Científicas com Processadores Heterogéneos", InForum 2011: Proceedings of InForum Simpósio de Informática, Coimbra, Universidade do Coimbra, 2011. Abstractinforum-pitxyoki.pdf

Actualmente o mercado residencial de computadores inclui não só multiprocessadores com diversos núcleos (CPUs) como também placas gráficas (GPUs) cuja capacidade de processamento tem evoluído a um ritmo exponencial. Este poder computacional pode ser utilizado para outros fins para além do processamento gráfico, tal como o processamento de algoritmos comuns em computação científica. Neste artigo é apresentada, discutida e avaliada a framework Cheetah, uma framework que distribui programas computacionalmente exigentes sobre uma rede de CPUs e GPUs. Um programador que utilize a Cheetah apenas necessita de especificar o seu programa como um conjunto de kernels OpenCL, relegando para a framework a distribuição destes pelas unidades de processamento disponíveis. O programa pode assim escalar à medida que são adicionados novos recursos computacionais, sem quaisquer esforços adicionais de adaptação ou recompilação. Os testes realizados demonstraram a capacidade de a framework providenciar aceleracçõs até duas ordens de grandeza com um esforço de desenvolvimento reduzido, mesmo quando na presença de recursos computacionais limitados.

Sousa, D. G., J. M. and Lourenço, E. Farchi, and I. Segall, "Aplicação do Fecho de Programas na Deteção de Anomalias de Concorrência", INForum 2012: Proceedings of INForum Simpósio de Informática, Monte de Caparica, PT, Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa, 6 Sep., 2012. Abstractinforum-closure.pdf

Uma das estratégias para tirar partido dos múltiplos processadores disponíveis nos computadores atuais passa por adaptar código legado, inicialmente concebido para ser executado num contexto meramente sequencial, para ser agora executado num contexto multithreading. Nesse processo de adaptação é necessário proteger apropriadamente os dados que são agora partilhados e acedidos por diferentes threads concorrentes. A proteção dos dados com locks usando uma granulosidade grossa inibe a concorrência e opõe-se ao objetivo inicial de explorar o paralelismo suportado por múltiplos processadores. Por outro lado, a utilização de uma granulosidade fina pode levar à ocorrência de anomalias próprias da concorrência, como deadlocks e violações de atomicidade (high-level data races). Este artigo discute o conceito de fecho de um programa e uma metodologia que, quando aplicados em conjunto, permitem adaptar código legado para o tornar thread-safe, garantindo a ausência de violações de atomicidade na versão corrente do software e antecipando algumas violações de atomicidade que poderão ocorrer em versões futuras do mesmo software.

Silva, J., J. M. Lourenço, and H. Paulino, "Boosting Locality in Multi-version Partial Data Replication", Proceedings of the 30th ACM/SIGAPP Symposium On Applied Computing (SAC'15), 2015. Abstractsac15_cache.pdf


Preguiça, N., R. Rodrigues, C. Honorato, and J. M. Lourenço, "Byzantium: Byzantine-fault-tolerant database replication providing snapshot isolation", Proceedings of the Fourth conference on Hot topics in system dependability, Berkeley, CA, USA, USENIX Association, pp. 9–9, 2008. Abstractbyzantium-hotdep.pdf

Database systems are a key component behind many of today's computer systems. As a consequence, it is crucial that database systems provide correct and continuous service despite unpredictable circumstances, such as software bugs or attacks. This paper presents the design of Byzantium, a Byzantine fault-tolerant database replication middleware that provides snapshot isolation (SI) semantics. SI is very popular because it allows increased concurrency when compared to serializability, while providing similar behavior for typical workloads. Thus, Byzantium improves on existing proposals by allowing increased concurrency and not relying on any centralized component. Our middleware can be used with off-the-shelf database systems and it is built on top of an existing BFT library.

Alves, A., F. P. Birra, and J. M. Lourenço, "Como separar o trigo do joio? Ou: Como selecionar a melhor fotografia de um conjunto de fotografias semelhantes", Proceedings of INForum Simpósio de Informática, Covilhã, Portugal, sep, 2015. Abstractinforum15-photo.pdf

O advento da fotografia digital está na base de uma clara mudança de paradigma no processo de gestão da fotografia por amadores. Porque tirar mais uma fotografia agora não representa qualquer custo adicional, é frequente tirarem-se múltiplas fotografias ao mesmo sujeito, na expectativa de que uma delas corresponda aos padrões de qualidade desejados, em termos de iluminação, foco e enquadramento. Assumindo que a questão do enquadramento se resolve facilmente recorrendo ao recorte (crop) da fotografia, tem-se ainda assim que selecionar qual das várias fotografias bem enquadradas, tecnicamente parecidas em termos de iluminação e foco, vamos guardar (e por oposição quais vamos descartar). A escolha da melhor fotografia com base na observação visual em ecrã de computador é um processo muito pouco preciso e, portanto, gerador de sensações de insegurança que resultam, muitas vezes, na opção de não descartar nenhuma das várias fotografias semelhantes. Neste artigo propomo-nos endereçar a questão de como ajudar um fotógrafo amador a selecionar a melhor fotografia de um conjunto de fotografias semelhantes em termos técnicos (foco e iluminação) e de enquadramento. Este processo é baseado num workflow suportado por um pacote de software, que com alguma ajuda do utilizador permite ordenar um conjunto de fotografias semelhantes, sendo assim possível escolher aquela que melhor corresponde às expectativas e dando segurança e conforto na eventual eliminação das restantes.

Cunha, G., J. Lourenço, and R. J. Dias, "Consistent State Software Transactional Memory", IV Jornadas de Engenharia de Electrónica e Telecomunicações e de Computadores (JETC'08), Lisboa, Portugal, ISEL - Instituto Superior de Engenharia de Lisboa, pp. 251–256, 2008. Abstractjetc_2008.pdf

Software transactional memory (STM) is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to memory (RAM) locations. In this paper we propose a new classification for the active states of a transaction; a new memory quiescing algorithm, to allow the safe transition of a memory block form transactional to non-transactional space; we compare word and object transactional grain units; and evaluate the cost of consistent state validation, arguing that this cost can be minimized by performing partial validation on problematic code regions.

Silva, J. A., H. Paulino, and J. M. Lourenço, "Crowd-Sourcing Mobile Devices to Provide Storage in Edge-Clouds", Proceedings of the Doctoral Symposium of the 16th International Conference on Distributed Computing and Networking, Jan, 2015. Abstracticdcn15srf.pdf

Given the proliferation and enhanced capabilities of mobile devices, their computational and storage resources can now be combined in a wireless cloud of nearby mobile devices, a mobile edge-cloud. These clouds are of particular interest in low connectivity scenarios, e.g., sporting events and disaster scenarios. In these dynamic clouds it is necessary to reliably disseminate and share data, and also to offload data processing computations to other devices in the edge-cloud. We are particularly interested in supporting storage services in these new type of edge-clouds, as a mean to enable data sharing, dissemination and querying, as well as to serve as a distributed file system for offloaded computations. In this Ph.D. thesis, we propose to address these questions by researching on the usage of ad-hoc clouds of mobile devices to develop an efficient storage service capable of providing high availability and reliability.

Cunha, J. C., J. M. Lourenço, and T. Antão, "A Debugging Engine for a Parallel and Distributed Environment", Proceedings of the 1st Austrian-Hungarian Workshop on Distributed and Parallel Systems (DAPSYS'96), Wien, Austria, Hungarian Academy of Sciences, KFKI, pp. 111–118, 1996. Abstractdapsys96.pdf

This paper describes a debugging interface that has been developed for a parallel software engineering environment and that was developed on top of the PVM environment in the scope of the SEPP and HPCTI projects of the COPERNICUS Program. The main goal of this interface is to provide the basic debugging functionalities that are required by some components of that environment. We give special attention to the requirements posed by high-level tools of the environment, and to the need of providing a flexible debugging support layer that can be suitably adapted and extended. We present the system logical architecture and the interface specification of the debugging engine. We discuss its interfacing with other components of the environment, namely a graphical editor for the GRAPNEL visual parallel programming language, and a testing tool. We finally describe current work on the improvement of the debugging engine. Keywords: Debugging, monitoring, parallel processing, software tools.

Teixeira, B., J. M. Lourenço, E. Farchi, R. J. Dias, and D. Sousa, "Detection of Transactional Memory Anomalies using Static Analysis", Proceedings of the 8th Workshop on Parallel and Distributed Systems: Testing, Analysis, and Debugging (PADTAD'10), New York, NY, USA, ACM, pp. 26–36, 2010. Abstractpadatad-teixeira-2010.pdf

Transactional Memory allows programmers to reduce the number of synchronization errors introduced in concurrent programs, but does not ensures its complete elimination. This paper proposes a pattern matching based approach to the static detection of atomicity violation, based on a path-sensitive symbolic execution method to model four anomalies that may affect Transactional Memory programs. The proposed technique may be used to to bring to programmer's attention pairs of transactions that the programmer has mis-specified, and should have been combined into a single transaction. The algorithm first traverses the AST tree, removing all the non-transactional blocks and generating a trace tree in the path sensitive manner for each thread. The trace tree is a Trie like data structure, where each path from root to a leaf is a list of transactions. For each pair of threads, erroneous patterns involving two consecutive transactions are then checked in the trace tree. Results allow to conclude that the proposed technique, although triggering a moderate number of false positives, can be successfully applied to Java programs, correctly identifying the vast majority of the relevant erroneous patterns.

Dias, R. J., J. Lourenço, and G. Cunha, "Developing Libraries Using Software Transactional Memory", CoRTA 2008: Proceedings of the Conference on Compilers, Related Technologies and Applications, Bragança, Portugal, Instituto Politécnico de Bragança - ESTG, 2008. Abstractcorta_2008.pdf

Software transactional memory (STM) is a promising programming model that adapts many concepts borrowed from the databases world to control concurrent accesses to main memory (RAM) locations. This paper aims at discussing how to support apparently irreversible operations within a memory transaction.

Cunha, J. C., J. M. Lourenço, and T. Antão, "A Distributed Debugging Tool for a Parallel Software Engineering Environment", Proceedings of the 1st European Parallel Tools Meeting (EPTM'96), Paris, France, ONERA (French National Establishment for Aerospace Research), October, 1996. Abstracteptm96.pdf

We discuss issues in the design and implementation of a flexible debugging tool and its integration into a parallel software engineering environment.

Cunha, J. C., P. D. Medeiros, J. M. Lourenço, V. Duarte, J. Vieira, B. Moscão, D. Pereira, and R. Vaz, "The DOTPAR Project: Towards a Framework Supporting Domain Oriented Tools for Parallel and Distributed Processing", Proceedings of the International Conference and Exhibition on High-Performance Computing and Networking (HPCN'98), London, UK, Springer-Verlag, pp. 952–954, 1998. Abstractdotpar98.pdf

We discuss the problem of building domain oriented environments by a composition of heterogeneous application components and tools. We describe several individual tools that support such environments, namely a distributed monitoring and control tool (DAMS), a process-based distributed debugger (PDBG) and a heterogeneous interconnection model (PHIS). We discuss our experience with the development of a Problem Oriented Environment in the domain of genetic algorithms, obtained by a composition of heterogeneous tools and application components.

Fiedor, J., Z. Letko, J. M. Lourenço, and T. Vojnar, "Dynamic Validation of Contracts in Concurrent Code", Proceedings of the Fifteenth International Conference on Computer Aided Systems Theory (EUROCAST'15), Las Palmas de Gran Canaria, Spain, Universidad de Las Palmas de Gran Canaria, 2015. Abstracteurocast15.pdf

Multi-threaded programs allow one to achieve better performance by doing a lot of work in parallel using multiple threads. Such parallel programs often contain code blocks that a thread must execute atomically, i.e., with no interference from the other threads of the program. Failing to execute these code blocks atomically leads to errors known as atomicity violations. However, frequently it not obvious to tell when a piece of code should be executed atomically, especially when that piece of code contains calls to some third-party library functions, about which the programmer has little or no knowledge at all. One solution to this problem is to associate a contract with such a library, telling the programmer how the library functions should be used, and then check whether the contract is indeed respected. For contract validation, static approaches have been proposed, with known limitations on precision and scalability. In this paper, we propose a dynamic method for contract validation, which is more precise and scalable than static approaches.

Dias, R. J., J. M. Lourenço, and N. Preguiça, "Efficient and Correct Transactional Memory Programs Combining Snapshot Isolation and Static Analysis", Proceedings of the 3rd USENIX Conference on Hot Topics in Parallelism (HotPar'11), Berkeley, USA, Usenix Association, May, 2011. Abstracthotpar2011.pdf

Concurrent programs may suffer from concurrency anomalies that may lead to erroneous and unpredictable program behaviors. To ensure program correctness, these anomalies must be diagnosed and corrected. This paper addresses the detection of both low- and high-level anomalies in the Transactional Memory setting. We propose a static analysis procedure and a framework to address Transactional Memory anomalies. We start by dealing with the classic case of low-level dataraces, identifying concurrent accesses to shared memory cells that are not protected within the scope of a memory transaction. Then, we address the case of high-level dataraces, bringing the programmer's attention to pairs of memory transactions that were misspecified and should have been combined into a single transaction. Our framework was applied to a set of programs, collected form different sources, containing well known low- and high-level anomalies. The framework demonstrated to be accurate, confirming the effectiveness of using static analysis techniques to precisely identify concurrency anomalies in Transactional Memory programs.

Dias, R. J., T. M. Vale, and J. M. Lourenço, "Efficient Support for In-Place Metadata in Transactional Memory", Proceedings of the 18th International Euro-Par Conference on Parallel Processing, Berlin, Heidelberg, Springer-Verlag, 2012. Abstracteuropar12.pdf

Software Transactional Memory (STM) algorithms correctness rely on metadata associated with the memory locations accessed during the transaction life-time. STM implementations may store this metadata either in-place, by wrapping the memory cells in a container that includes the memory cell itself and the corresponding metadata, or out-place, by resorting to a mapping function that associates the memory cell address to an external table with the corresponding metadata. The implementation techniques for these two approaches are very different and each STM framework is usually biased towards one of them, only allowing the efficient implementation of algorithms that fall into the appropriate category, and inhibiting the fair comparison with STM algorithms falling into the other. In this paper we introduce a technique that supports the use of in-place metadata without requiring to wrap memory cells, thus providing STM algorithms with direct access to the transactional metadata and overcoming the bias. The proposed technique is available as an extension to the DeuceSTM framework and allows the efficient implementation of a wide range of STM algorithms, thus enabling their fair (unbiased) comparison in a common STM infrastructure. We illustrate the benefits of our approach by analyzing its impact in two popular TM algorithms with two different transactional workloads, TL2 and multi-versioning, which bias to out-place and in-place respectively.